ESD E.1104.02, Руководство по оборудованию, Страница: 19 / 26

Technical Data
6.3 FPGA
Type Altera Cyclone V GX, FBGA 484, 50K LE CGXFC4C7F23C8N
IP-core Beckhoff
®
IP-core
- contains 60 kByte ESC DPRAM
- supports 64 bit timestamps (for DC, Sync and Latch values)
- supports 8 EtherCAT SyncManagers
- supports 8 EtherCAT FMMUs
Table 5: FPGA
6.4 PCI Bus Interface
Host bus PCI-Bus according to PCI Local Bus Specification 3.0
PMC specification IEEE Standard 1386.1-2001
PCI bus master
capability yes
PCI-data bus 32 bit
PCI bus clock rate 66 MHz / 3.3 V signal level
33 MHz /3.3 V signal level or 5 V signal level Universal board
Interrupt Interrupt signal A, B, C (automatically configured)
Connector via PMC Pn1, Pn2 and Pn4 according to IEEE Standard 1386.1-2001
Device ID / Vendor ID constant, 0x0703 / 0x12FE
Subsystem Device ID /
Subsystem Vendor ID 0x0703 /
0x12FE as endpoint
Revision ID 0x0001
Class Code 0x28000
Table 6: Data of the PCI bus
6.5 Ethernet Interface
Number 1
Standard 100BASE-TX, 100Mbit/s according to IEEE 802.3
Controller EtherCAT Slave Controller Beckhoff IP Core integrated in FPGA
+ 2x MII Phy (Micrel KSZ8081MNX)
Electrical isolation via transformer,
2.5 mm creepage distance,
1500 Vrms / 2250 VDC
Ports IN and OUT
Connector 2 x RJ45 socket with separate LEDs for status indication (see “LED
Indication” page 14)
Table 7: Data of the EtherCAT interface
ECS-PMC/FPGA Hardware Manual • Doc. No.: E.1104.21 / Rev. 1.1 Page 19 of 26