Overview
2. Overview
Figure 6:
Block circuit diagram of ECS-PMC/FPGA
The ECS-PMC/FPGA is an EtherCAT Slave Controller Board in a IEEE 1386.1 (PMC) form factor.
It utilizes a Beckhoff
®
IP-core which is implemented in an Altera
®
FPGA and configured for
8 FMMUs, 8 Sync managers, 60 kB DPRAM and 64 bit Distributed Clocks.
Other configurations are available on request.
The FPGA connects between the PCI bus on the PMC P11 and P12 connectors and the two
Ethernet interfaces on the front panel.
The additional EtherCAT signals SYNC and Latch are available on the PMC I/O connector P14.
The FPGA contains Bus Master DMA support to offload the CPU from copying the output process
image data into the host memory. This is utilized by the esd EtherCAT Slave Stack.
Because of this simple hardware topology and the use of a “soft” controller the design offers a
maximum of flexibility.
The PMC system can act as an I/O node. An EtherCAT master can use several EtherCAT
protocols like CoE, FoE and EoE to communicate with this EtherCAT slave device.
Via connector PMC-P14 equipped on the ECS-PMC/FPGA 16 3.3 V-LVTTL I/Os are available,
including the signals from the EtherCAT slave controller: 2x Sync and 2x Latch.
Device drivers for Windows® and Linux® with documentation and EtherCAT slave examples are
included in the scope of delivery. Drivers for other operating systems, especially real-time OS, are
available on request.
Page 12 of 26
Hardware Manual • Doc. No.: E.1104.21 / Rev. 1.1
ECS-PMC/FPGA
I²C
SPI-Flash
up to
16MByte
Ethernet
Phy
10/100
PCIe
1
JTAG
Front LED
6
0R
Ethernet
Phy
10/100
Temp.
Sensor
Status
2
Status
2
MII
MII
EEPROM
32KBit
I²C
Serial No.
FPGA
RJ45
RJ45
PCIe to PCI
Bridge
P
M
C
-P
14
P
M
C
-P
11
P
M
C
-P
12
LVTTL-IO
SPI