Overview
1. Overview
1.1 Description of the Module
Figure 1:
Block circuit diagram of CAN-PCI/400
The CAN-PCI/400 is a PC board designed for the PCI bus that features two (CAN-PCI/400-2) or
optionally four (CAN-PCI/400-4) electrically isolated CAN High-Speed interfaces according to ISO
11898-2. CAN-PCI/400-4 comes with two additional CAN interfaces via a separate slot bracket.
The independent CAN nets acc. to ISO 11898-1 are driven by the esdACC (esd Advanced CAN
Core) implemented in the Xilinx
®
Spartan
®
-3E FPGA. Controlled by the FPGA the CAN-PCI/400
supports bus mastering as an initiator, meaning that it is capable of initiating write cycles to the
host CPU’s RAM independent of the CPU or the system DMA controller. This results in a reduction
of overall latency on servicing I/O transactions in particular at higher data rates and reduced host
CPU load.
The CAN-PCI/400 provides high resolution hardware timestamps.
CAN Error injection on request.
CAN layer 2 (NTCAN-API) software drivers are available for Windows
®
, VxWorks
®
, QNX
®
, RTX
®
and Linux
®
supporting up to 24 CAN nets. Drivers for other operating systems are available on
request. The CANopen software package is available for Windows, Linux, VxWorks, and QNX.
Page 8 of 29
Hardware Manual • Doc. No.: C.2048.21 / Rev. 1.1
CAN-PCI/400
FPGA
Xilinx Spartan-3E
(32-Bit Microcontroller
MicroBlaze Option)
PCI Bridge
PLX PCI 9056
RAM
(Option)
C
A
N
B
U
S
Physical
CAN
Layer
C
A
N
B
U
S
Physical
CAN
Layer
CAN2
CAN3
CAN0
CAN1
DSUB9
CiA pinning
DSUB9
CiA pinning
4 x
CAN Core
with Timestamp
PCI
Card Edge
Connector
DC/DC
Converter
DC/DC
Converter
Adapter Board (CAN-PCI/400-4 only)
Option
10-pole
post connector
CAN-adapter board
Electrical Isolation
Electrical Isolation
Ribbon
Cable
