ROK 101 007
8
Preliminary
Pin Description
Pin
Pin Name
Type
Direction
Description
A1
PCM_IN
CMOS
In
PCM data, see notes 7,9
A2
PCM_OUT
CMOS
Out
PCM data, see notes 7,9
A3
PCM_SYNC
CMOS
In/Out
Sets the PCM data sampling rate, see notes 7,9
A4
PCM_CLK
CMOS
In/Out
PCM clock that sets the PCM data rate, see notes 7,9
A5
RXD
CMOS
Input
RX data to the UART, see note 9
A6
RTS
CMOS
Input
Flow control signal, Request To Send data from UART, see notes 7,9
B1
D+
CMOS
In/Out
USB data pin, see notes 9,10
B2
D-
CMOS
In/Out
USB data pin, see notes 9,10
B3
GND
Power
Power
Signal ground
B4
WAKE_UP
CMOS
Output
Indicates that the module wants to be attached to the USB,
Active High. See notes 9,10
B5
TXD
CMOS
Output
TX data from the UART, see note 9
B6
CTS
CMOS
Output
Flow control signal, Clear To Send data from UART, see note 9
C1
DETACH
CMOS
Input
Indicates that the USB host wants to detach the module,
Active High. See notes 7,9
C2
ON
Power
Input
When tied to V
CC
, the module is enabled.
C3
I2C_CLK
CMOS
Output
I2C clock signal, see note 9
C4
VCC_IO
Power
Power
External supply rail to the Input / Output ports
C5
NC
-
-
Do not connect
C6
VCC
Power
Power
Supply Voltage
R1
GND
Power
Power
Signal ground
R2
GND
Power
Power
Signal ground
R3
RESET#
CMOS
Input
Active low reset, see notes 8,9
R4
NC
-
-
Do not connect
R5
NC
-
-
Do not connect
R6
NC
-
-
Do not connect
T1
GND
Power
Power
Signal Ground
T2
ANT
RF
In/Out
50
Ω
Antenna connection
T3
GND
Power
Power
Signal Ground
T4
NC
Power
Power
Test point, internal voltage regulator - Do not connect
T5
NC
-
-
Do not connect
T6
I2C_DATA
CMOS
In/Out
I2C data signal, see note 9
Notes
1. Current consumption is based upon when the module is when ‘ON’ is low and ‘VCC_IO’ is grounded.
2. During the TX mode, the VSWR specification states the limits that are acceptable before any other RF parameters
are strongly effected, i.e. frequency deviation and initial frequency error.
3. Frequency deviation measurements are now recorded differentially, (f Mod1 - f Mod0 ) / 2.
4. Provided that the TX INV register (bit 0) has been set in the enable register at startup.
5. Tolerance for the system clock takes into account both the complete temperature range and aging of the crystal.
6. LPO_CLK frequency is pre-trimmed within a tolerance of
±
250ppm.
7. 100k
Ω
pull-up resistors to V
CC_IO
are used on the module. PCM signals direction is programmable
8. RESET# signal must be fed from an open drain output.
9. CMOS buffers are low voltage TTL compatible signals.
10. To be compliant with the USB specification, VCC_IO
≥
3.11V