Ericsson 9D902780G3, Руководство по обслуживанию

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LOGIC CIRCUITS
Logic circuitry (other than that inside the synthesizer IC -
U402) consists of the following:
•
An address decoder
•
Input gates and level shifters
•
Lock Indicator circuitry
The address decoder, U702, enables the Input Gates when
the A0, A1, and A2 input lines receive the proper logic code
(110 for the transmitter synthesizer). After receiving the proper
code, Y3 (U702-12) sends a logic low signal to U701C. U701C
acts as an inverter and uses the logic high output to turn on
Input Gates U701A, U701B, and U701D. The Input Gates
allow the clock, data and enable information to pass on to the
synthesizer via the level shifters. The Level Shifter Transistors
Q701, Q702 and Q703 convert the 5 volt gate logic level to the
8 volt logic level required by the synthesizer U402.
The Fault Indicator circuitry indicates when the synthesizer
is in an out-of-lock condition. The fault detector latches,
U705A and U705B are reset by the enable pulse during initial
loading of data into the synthesizer. If at any time afterwards
the lock detector signal (LD) goes low, the high output of
U705B will cause the output of gates U705C and U705D to go
low. The low output from U705C causes Q704 to conduct
turning on the front panel LED (CR701). The output of U705D
(FLAG) is connected to J3-13C for external monitoring of the
Synthesizer Module. A logic low on the FLAG line indicates
an out-of-lock condition.
MAINTENANCE
RECOMMENDED TEST EQUIPMENT
The following test equipment is required to test the synthe-
sizer Module:
1. RF signal source for 12.8 MHz, 0 dBm reference (in-
cluded with item 10)
2. AF Generator or Function Generator
3. Modulation Analyzer; HP 8901A, or equivalent, or a
UHF receiver
4. Oscilloscope; 20 MHz
5. DC Meter; 10 meg ohm (for troubleshooting)
6. Power Supply; 13.8 Vdc @ 350 mA
12.0 Vdc @ 25 mA
7. Spectrum Analyzer; 0-1 GHz
8. Frequency Counter; 10 MHz - 500 MHz
9. Personal Computer (IBM PC compatible) to load fre-
quency data
10. Service Parts Kit, (TQ-0650), (includes software for
loading frequency data)
TEST PROCEDURE
(Steps 5, 6, and 7 can be done using a modulation
analyzer or UHF receiver with 750
µ
s de-emphasis switch-
able in or out.
1. Lock synthesizer at 470.0 (G3), 430 (G6), 450 (G7),
400 (G8), or 494 (G9) MHz using software provided
in the service parts kit.
Verify lock (flag = high).
Verify front panel LED is off.
2. Measure output frequency.
Verify frequency = 470.0000 (G3), 425.000
(G6) or 450.000 (G7) MHz, 400.000 (G8), or
494.000 (G9)
±
200 Hz.
3. Measure harmonic content.
Verify 2nd harmonic is < -30 dBc.
4. Measure RF power output into 50 ohm load.
Verify 10 to 13 dBm (10 to 20 mW).
5. Measure AF distortion with standard modulating sig-
nal input.
Verify <5%.
6. Measure Hum and Noise relative to 0.44 kHz average
deviation, (de-emphasis on).
Verify < -55dB
7. Measure AF response at 300 Hz, 1 kHz (ref) and 3
kHz, (de-emphasis off).
Verify within
±
1.5 dB with respect to 1 kHz
reference.
8. Verify lock at different frequencies.
a. Lock synthesizer at 380 (G8), 450 (G3), 403
(G6), 425 (G7), or 470 (G9) MHz. Verify LED
is off.
b. Lock synthesizer at 385 (G8), 455 (G3), 408.5
(G6), 430 (G7), or 476 (G9) MHz. Verify LED
is off.
c. Lock synthesizer at 390 (G8), 460 (G3), 414
(G6), 437.5 (G7), or 482 (G9) MHz. Verify
LED is off.
d. Lock synthesizer at 395 (G8), 465 (G3), 419.5
(G6), 445 (G7), or 488 (G9) MHz. Verify LED
is off.
ALIGNMENT PROCEDURE
1. Apply +13.8 Vdc and -12 Vdc. Verify the current
drain on the 13.8 volt supply is, <300mA and the
current drain on the -12 volt supply is <20 mA.
2. Lock the synthesizer at 380 (G8), 450 (G3), 403 (G6),
425 (G7), or 470 (G9) MHz. Adjust trimmer C1O
until Vtest (23A) reads 2.5 (G3, G8), or 2.0 (G6, G7,
G9) V
±
0.05V.
3. Lock synthesizer at 460.0 (G3), 390.0 (G8), 414 (G6)
or 437.5 (G7), or 482 (G9) MHz for the following
three adjustments.
•
Set VR602 for 4.5 kHz peak deviation with a stand-
ard modulating signal applied to the audio input.
•
Set VR601 for 4.4 kHz peak deviation with 0.6
Vrms, 10 Hz sine wave audio applied to module AF
input.
•
Apply a 10 Hz 0.85 Vpk square wave (same peak
value as 0.6 rms (sine wave) to module AF input.
Adjust VR601 slightly for the flattest demodulated
square wave using a modulation analyzer or re-
ceiver (no de-emphasis) and an oscilloscope. The
maximum net variation in voltage over 1/2 cycle is
10%.
TROUBLESHOOTING
A troubleshooting guide is provided showing typical
measurements at the various test points.
SERVICE NOTES
The following service information applies when
aligning, testing, or troubleshooting the TX Synthe-
sizer:
•
Standard Modulating Signal = 1 kHz sinusoidal
voltage, 0.6 Vrms at the module input terminals
(600 ohm R
in
).
•
Logic Levels:
Logic 1 = high = 4.5 to 5.5 Vdc
Logic 0 = Low = 0 to 0.5 Vdc
•
Transmitter Synthesizer Address = A0 A1 A2 =
110
•
Synthesizer data input stream is as follows:
14-bit "R" divider most significant bit
(MSB) = R13 through "R" divider least sig-
nificant bit (LSB) = R0
10-bit "N" divider MSB = N9 through "N"
divider LSB = N0
7-bit "A" divider MSB = A6 through "A"
divider LSB = A0
Single high Control bit (last bit)
Latched When Control Bit = 1
DATA ENTRY FORMAT
Latched When
Control Bit = 1
Data in
➞
Last A0 A6 N0 N9 R0 R13
➞
Bit LSB – – – – – MSB LSB – – – – MSB LSB
For the transmitter synthesizer, 5 kHz chan-
nel spacing
R = 2560
N = integer part of (frequency in kHz)/(320)
A = (frequency in kHz)/(5) - 64*N
All numbers must be converted to binary.
•
ANT_REL line must be logic low (0V) in order to
lock synthesizer.
•
Synthesizer lock is indicated by the extinguishing
of the front panel LED indicator and a logic high
on the fault flag line (J3 pin 13C).
•
Always verify synthesizer lock after each new data
loading.
Control B
LBI-38671
3