Installation and Configuration
8
Seiko Epson Corporation
S5U13A05P00C100 Evaluation Board
Rev. 1.02
All S1D13A05 configuration inputs are fully configurable using the eight position DIP
switch as described below.
Table 3-1: Configuration DIP Switch Settings
Switch
(SW1)
S1D13A05
Signal
Value on this pin at rising edge of RESET# is used to configure:
Closed (On/1)
Open (Off/0)
SW1-5,
SW1-[3:1]
CNF4,
CNF[2:0]
Select host bus interface as follows:
CNF4 CNF2
CNF1
CNF0
Host Bus Interface
1
0
0
0
SH-4/SH-3 interface, Big Endian
0
0
0
0
SH-4/SH-3 interface, Little Endian
1
0
0
1
MC68K #1, Big Endian
0
0
0
1
Reserved
1
0
1
0
MC68K #2, Big Endian
0
0
1
0
Reserved
1
0
1
1
Generic #1, Big Endian
0
0
1
1
Generic #1, Little Endian
1
1
0
0
Reserved
0
1
0
0
Generic #2, Little Endian
1
1
0
1
RedCap 2, Big Endian
0
1
0
1
Reserved
1
1
1
0
DragonBall, Big Endian
0
1
1
0
Reserved
X
1
1
1
Reserved
SW1-4
CNF3
Reserved. Must be set to 1.
SW1-6
CNF5
WAIT# is active high
WAIT# is active low
SW1-7
CNF6
CLKI to BCLK Divide ratio 2:1
CLKI to BCLK divide ratio 1:1
SW1-8
-
Disable PCI bridge for non-PCI host
Enable PCI bridge for PCI host
= Required settings when using the PCI Bridge FPGA
