Epson S5U13A05P00C100, Руководство пользователя

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LCD Interface Pin Mapping
14 Seiko Epson Corporation
S5U13A05P00C100 Evaluation Board
Rev. 1.02
5 LCD Interface Pin Mapping
Note
1
These pin mappings use signal names commonly used for each panel type, however
signal names may differ between panel manufacturers. The values shown in brackets
represent the color components as mapped to the corresponding FPDATxx signals at
the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see
S1D13A05 Hardware Functional Specification , document number X40A-A-001-xx.
2
GPO0 can be inverted on H1 by setting JP5 to 2-3.
Table 5-1: LCD Connector (H1)
Pin
Name
H1
Pin
No.
Monochrome
Passive Panel
Color Passive Panel Color TFT Panel
Single
Single
Others
Sharp
HR-TFT
Casio
TFT
TFT
Type 2
TFT
Type 3
TFT
Type 4
Format
1
Format
2
4-bit 8-bit 4-bit 8-bit 8-bit 16-Bit 9-bit 12-bit 18-bit 18-bit 18-bit 18-bit 18-bit 18-bit
FPDAT0 1 driven 0 D0 driven 0 D0 (B5)
1
D0 (G3)
1
D0 (R6)
1
R2 R3 R5 R5 R5 R5 R5 R5
FPDAT1 3 driven 0 D1 driven 0 D1 (R5)
1
D1 (R3)
1
D1 (G5)
1
R1 R2 R4 R4 R4 R4 R4 R4
FPDAT2 5 driven 0 D2 driven 0 D2 (G4)
1
D2 (B2)
1
D2 (B4)
1
R0 R1 R3 R3 R3 R3 R3 R3
FPDAT3 7 driven 0 D3 driven 0 D3 (B3)
1
D3 (G2)
1
D3 (R4)
1
G2 G3 G5 G5 G5 G5 G5 G5
FPDAT4 9 D0 D4 D0 (R2)
1
D4 (R3)
1
D4 (R2)
1
D8 (B5)
1
G1 G2 G4 G4 G4 G4 G4 G4
FPDAT5 11 D1 D5 D1 (B1)
1
D5 (G2)
1
D5 (B1)
1
D9 (R5)
1
G0 G1 G3 G3 G3 G3 G3 G3
FPDAT6 13 D2 D6 D2 (G1)
1
D6 (B1)
1
D6 (G1)
1
D10 (G4)
1
B2 B3 B5 B5 B5 B5 B5 B5
FPDAT7 15 D3 D7 D3 (R1)
1
D7 (R1)
1
D7 (R1)
1
D11 (B3)
1
B1 B2 B4 B4 B4 B4 B4 B4
FPDAT8 17 driven 0 driven 0 driven 0 driven 0 driven 0 D4 (G3)
1
B0 B1 B3 B3 B3 B3 B3 B3
FPDAT9 19 driven 0 driven 0 driven 0 driven 0 driven 0 D5 (B2)
1
driven 0 R0 R2 R2 R2 R2 R2 R2
FPDAT10 21 driven 0 driven 0 driven 0 driven 0 driven 0 D6 (R2)
1
driven 0 driven 0 R1 R1 R1 R1 R1 R1
FPDAT11 23 driven 0 driven 0 driven 0 driven 0 driven 0 D7 (G1)
1
driven 0 driven 0 R0 R0 R0 R0 R0 R0
FPDAT12 25 driven 0 driven 0 driven 0 driven 0 driven 0 D12 (R3)
1
driven 0 G0 G2 G2 G2 G2 G2 G2
FPDAT13 27 driven 0 driven 0 driven 0 driven 0 driven 0 D13 (G2)
1
driven 0 driven 0 G1 G1 G1 G1 G1 G1
FPDAT14 29 driven 0 driven 0 driven 0 driven 0 driven 0 D14 (B1)
1
driven 0 driven 0 G0 G0 G0 G0 G0 G0
FPDAT15 31 driven 0 driven 0 driven 0 driven 0 driven 0 D15 (R1)
1
driven 0 B0 B2 B2 B2 B2 B2 B2
FPDAT16 4 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 B1 B1 B1 B1 B1 B1
FPDAT17 6 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 B0 B0 B0 B0 B0 B0
FPSHIFT 33 FPSHIFT DCLK CLK CLK CPH FPSHIFT
DRDY
35 &
38
MOD
FPSHIFT2
MOD DRDY driven 0
no
connect
INV INV DRDY
FPLINE 37 FPLINE LP GPCK STB LP FPLINE
FPFRAME 39 FPFRAME SPS GSRT STV STV
FPFRAME
GND
2, 8,
14, 20,
26
GND
PWMOUT 28 PWMOUT
N/C 30 Not connected
LCDVCC 32 LCDVCC (3.3V or 5V)
+12V 34 +12V
N/C 36 Not Connected
GPO0
2
40 GPO0 (for controlling on-board LCD bias power supply on/off)