Technical Description
16
Seiko Epson Corporation
S5U13A05P00C100 Evaluation Board
Rev. 1.02
6 Technical Description
6.1 PCI Bus Support
The S1D13A05
does not
have on-chip PCI bus interface support. The S1D13A05P00C100
uses the on-board PCI Bridge FPGA to support the PCI bus.
6.2 Direct Host Bus Interface Support
The S5U13A05P00C100 is specifically designed to work using the PCI Bridge FPGA in a
standard PCI bus environment. However, the S1D13A05 directly supports many other host
bus interfaces. Connectors H4 and H5 provide the necessary IO pins to interface to these
host buses. For further information on the host bus interfaces supported, see “CPU
Interface” on page 11.
Note
If a direct host bus interface is used, the PCI Bridge FPGA must be disabled using
SW1-8.
6.3 S1D13A05 Embedded Memory
The S1D13A05 has 256K bytes of embedded SRAM. The 256K byte display buffer address
space is directly and contiguously available through the 18-bit address bus.
6.4 Software Adjustable LCD Backlight Intensity Support Using PWM
The S1D13A05 provides Pulse Width Modulation output on PWMOUT. PWMOUT can be
used to control LCD panels which support PWM control of the backlight inverter. The
PWMOUT signal is provided on LCD Connector H1.
