1
SUMMARY
S1C33 FAMILY C33 PE CORE MANUAL
EPSON
3
1
.
2
.
2
Registers
The general-purpose registers (R
0
to R
15
) are basically the same as in the C
33
STD Core CPU.
The special registers have been functionally extended as described below.
PC
All
32
bits can now be used.
Moreover, the PC can now be read out to enable high-speed leaf calls.
Trap table base register
A trap table base register (TTBR) has been added.
TTBR, which was mapped at address
0
x
48134
in the C
33
STD Core CPU, is incorporated in the C
33
PE Core
as a special register. The initial value (boot address) has not changed from
0
xC
00000
.
Processor identification register
A processor identification register (IDIR) has been added for identifying the core type and version.
Debug base register
A debug base register (DBBR) has been added. This register indicates the start address of the debug area. It
normally is fixed to
0
x
60000
.
Processor status register
The following flags in PSR have been removed as have the related instructions:
MO flag (bit
7
)
Mac overflow flag
DS flag (bit
6
)
Divide sign
1
.
2
.
3
Address Space and Other
Address space
The C
33
PE Core supports a
4
G-byte space based on a
32
-bit address bus.
Other
1
. Interrupt/exception processing
The Trap Table Base Register (TTBR) now serves as an internal special register of the processor.
Furthermore, this processor has come to generate an exception when an undefined instruction (an object
code not defined in the instruction set) is executed or more than two
ext
instructions are described.
2
. Pipeline
The
3
-stage pipeline in the C
33
STD Core CPU has been modified to a
2
-stage pipeline in the C
33
PE Core
(consisting of fetch/decode and execute/access/write back).
Содержание S1C33 Series
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