Endace Measurement Systems.
http://www.endace.com
EDM01.05-10r1 DAG 4.3S Card User Manual
2
Revision 6. 22 September 2005.
1.2 DAG 4.3S Card Product Description
Description
The DAG 4.3S card is designed only for PCI-X buses. It is capable of cell
and packet capture and generation on IP networks.
Figure
Figure 1-1 shows the DAG 4.3S series PCI-X card.
Figure 1-1. DAG 4.3S series PCI-X Card.
The DAG 4.3S card collects packet header and payload from ATM, POS,
and supports ATM, PPP HDLC, CISCO, HDLC over OC40c SONET or
SDH networks.
Full packet or cell capture at line rate allows recording of all header
information payload and with a high precision timestamp, subject to bus
and processor availability.
The DAG 4.3S is capable of transmitting packets at 100% line rate while
simultaneously receiving packets at 100% line rate.
1.3 DAG 4.3S Card Architecture
Description
Serial SONET optical network data received by optical interface flows
into a physical layer ASIC, then immediately into the Field-Programmable
Gate Array [FPGA].
The FPGA contains an Endace DAG Universal Clock Kit
[DUCK]
timestamp engine, packet record processor, and PCI-X interface logic.
Because of component close association, packets or cells are time-stamped
accurately. Time stamped packet records are stored in an external FIFO
memory before transmission to the host.
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