emCON-MX8MM - Hardware Manual (Rev1)
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The Boot medium is configured via a dip switch on the emCON MX8MM module.
emCON MX8MM CPU Module (SW1):
SW1
SW2
SW3
SW4
Configuration
OFF
OFF
ON
OFF
eMMC
Na.
Na.
Na.
Na.
SDC
Na.
Na.
Na.
Na.
QSPI
Configurations for other boot devices will be coming soon.
4.2
NAND Flash
To store the operating system and application data, an eMMC-NAND Flash is provided on the
emCON-MX8MM module. It is connected to the uSDHC1 controller of the i.MX8MM.
You can choose a NAND Flash size between 4GB and 32GB, depending on your requirements.
Please contact emtrion GmbH for your required NAND Flash size.
The onboard NAND Flash controller can be reset by
a logical “0”
on the GPIO1_IO03 Pin.
4.3
LPDDR4 SDRAM
LPDDR4 SDRAM is available as main memory. The RAM memory has a 32-bit width interface, a
density of 4GB and can be clocked up to 1865 MHz (3733 Mb/s).
Please contact emtrion GmbH for your required RAM size.
4.4
Ethernet
The Ethernet interface is realized with the processor internal Media Access Controller (MAC) and an
external Physical Layer Interface (PHY) KSZ9031RNX from Micrel. The RGMII interface is used for
communication between the MAC and the PHY.
The Ethernet interface supports the operating modes 10, 100 and 1000BASE-TX, all half- and full
duplex. HP Auto-MDIX is also supported.
The registers of the Ethernet PHY can be configured via the Media Independent Interface (MII).
The Ethernet signal lines (GBE1_MDIO[0:3]_P, GBE1_MDIO[0:3]_N) as well as two status signals,
indicating the link status and the transfer speed, are connected to the emCON connector. An
appropriate 1:1 transformer with a 100nF capacitor to GND at each center tap pin must be added
externally. The center tap pin shall not be supplied with 3.3V!
The emCON pins GBE1_LED_10_100# and GBE1_LED_1000# are both connected to the LED2 pin of
the Ethernet PHY and indicate if a link is established. (
“0”
= link). Therefore, the link speed has to be
determined by the software.
