Functional Description
NITX-300-ET-DVI Installation and Use (6806800N97A)
55
GPIO[4]
LPC[0] clock buffer strength control. Also muxed with WDT_TIMEOUT.
GPIO[3:2]
Defines CMC base address
GPIO[1]
Reserved
GPIO[0]
Defines boot flash from SPI or LPC
9 Sus well GPIOs accessible during S3 sleep state (GPIO SUS[0:8])
GPIO_SUS[8]
Defines number of ranks enabled
GPIO_SUS[6:5]
Defines memory device densities
GPIO_SUS[2]
Muxed with LVDS BKLTCTL
GPIO_SUS[1]
Muxed with LVDS BKLTEN
GPIO_SUS[0]
Defines memory device width (x16 or x8). Also muxed with LVDS VDDEN.
Table 4-4 Topcliff GPIO Configuration
Name
Function
GPIO0
USB MUX control.
Low: USB port5 is routing to Mini PCI-E slot
High : USB port5 is routing to eUSB slot
GPIO1
NC
GPIO2
NC
GPIO3
NC
GPIO4
NC
GPIO5
Client USB power detect.
Low: No Client USB power existence
High: Client USB power existence
GPIO6
NC
GPIO7
NC
GPIO8
DRAM vendor.
Low: SAMSUNG
High: MICRON
Table 4-3 TNC GPIO Definition (continued)
5 Core-well GPIOs (turned off during sleep mode)
Содержание NITX-300-ET-DVI
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