EMAC MicroPac 535, Справочник по аппаратуре

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MEMORY BANKING
The output of P5.0 is the A16 line for U11 and U12 (the RAM and EPROM/Flash, respectively). This allows the 80535 to access twice the
normal amount of memory. For example when P5.0=0, device addresses 0:0000-0:FFFF are selected, or when P5.0=1, device addresses
1:0000-1:FFFF are selected. This P5.0 only affects devices greater than 64K in size (smaller devices will select the same addresses
regardless of the value of P5.0).
Due to the 80535 architecture P5.0 is set to 1 when the CPU comes out of reset, which will select the upper 64K of the devices in U11 and
U12. For this reason, if the EPROM/Flash is larger than 64K in size, the initialization startup code (including vectors for RESET and the
interrupts) must reside starting at 1:0000 and if the 128K RAM option is installed, the external RAM device address range selected will be
1:0000-1:FFFF.
Care must be taken when writing applications which use both 128K of RAM and 128K EPROM/Flash. There must be instructions in the
bank to which you are switching. This is necessary not only when attempting to access another EPROM/Flash bank, but even when
accessing a different bank of RAM, since the EPROM/Flash and RAM banks are both switched by P5.0.
The solution is to use low level subroutines which are mirrored in the upper and lower banks of the EPROM/Flash, so that when a
subroutine changes the level of P5.0 it will switch seamlessly to the mirrored subroutine. For example, if there is a group of low level
subroutines residing at addresses 1:0000-1:0452 then the code should be duplicated also at 0:0000-0:0452. These subroutines could
handle bank switching to allow calling of routines in another bank, reading data memory, and reading/writing external RAM. When 128K
devices are used in both U11 and U12, the upper 64K of RAM can only be accessed by program code running in the upper 64K of
EPROM/Flash. Likewise the lower 64K of RAM can only be accessed by program code running in the lower 64K of EPROM/Flash.
Subroutines can be written, though, which will pass data to and from other banks via registers or internal CPU RAM.
RAM
The RAM socket U11 may be populated by 8K, 32K or 128K RAMs. Addresses 7FFF-FFFF of the external data memory allow full access
to the 8K or 32K devices.
When 128K RAMs are used, setting P5.1 will enable external data memory addresses 0000-7FFF to access the RAM, allowing a full 64K
of RAM to be accessed at one time. The output of P5.0 will select the upper or lower half of the device.
EPROM/Flash
The EPROM/Flash socket U12 may be populated by the following devices:
Description Part # Jumper setting
32K EPROM 27C256 (JP 1 Must be in the program/data configuration)
64K EPROM 27C512 (JP 1 Must be in the 64K-128K EPROM/Flash configuration)
128K EPROM 27C010 (JP 1 same as above)
64K Flash 29C512 (JP 1 same as above)
128K Flash 29C010 (JP 1 same as above)
128K Flash 29F010 (JP 1 same as above)
WRITING TO FLASH
To write to Flash JP 2 must be configured properly. JP2 has three specific settings:
Rev. 0,1 compatibility
o o-o B JP2
o o-o A
1 3 5 Flash RD/WR
o-o o B JP2
o-o o A
1 3 5 Flash WR protect
o o-o B JP2
o-o o A
1 3 5
The Rev. 0,1 compatibly setting allows software written for Rev. 0,1 boards to work on the current revision. The other two settings are for
Flash configuration. The Flash RD/WR setting allows for writing to the Flash under program control. In the situation where, perhaps, an