EMAC MicroPac 535, Справочник по аппаратуре

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APPENDIX E
MicroPac 535 Hardware Revision Notes
Revision 2: The majority of changes in this revision were necessary to implement the 128K Flash ROM capability.
JP2 was added to allow the rev. 2 hardware to be compatible with software written for rev. 0 and 1. With the jumper in the rev. 2
position all older software will work as on the older versions..
With JP2 in the Flash RD/WR mode position, P5.4 is no longer used to read the DO pin on the SEEPROM, and is now used as
a selector which exchanges the locations of the memory devices (this jumper position also connects DO to DI which requires different
SEEPROM drivers). On reset, P5.4 is high which puts the Flash in the code space and RAM in the external RAM space. When P5.4 is
brought low the Flash is accessed as if it were external RAM and the RAM is treated as code space.
An option was added to the PCB which allows P4 to drive a high current latch through invertors. If this option is not installed P4
works the same as in the previous revisions.
The SCC26C92 , the optional DUART, was changed from a 40 pin DIP package to a 44 pin PLCC.