Efinix Trion T120 BGA324, Руководство пользователя

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Trion T120 BGA324 Development Kit User Guide
Header J15 (RJ-45 Ethernet)
The board has a Gigabit Ethernet transceivers from Davicom (part number: DM9119IN,
which is compliant with IEEE Std. 802.33 MAC and IEEE STD. 802.3I 1000BASE-
TX/100BASE-TX/10BASE-T. The chip supports:
• Reduced Gigabit Media Independent Interface (RGMII) to the MAC controller
• Standard unshielded twisted pair (UTP) CAT6, CAT5e, CAT5, CAT3 cable (10 Mbps
only)
• Auto-negotiation with auto MDI/MDI crossover correction, auto polarity correction, and
power down mode
• Advanced DSP for baseline wander correction, equalization, echo, and crosstalk
cancellation
The Ethernet transceiver U18 is set to address 0x03H.
Table 17: J15 (Ethernet) Pin Assignments
Signal Name Pin Name T120F324I4 Name Description
ETH_GTXCLK GTXCLK GPIOL_72 GMII transmit clock
ETH_TXEN TXEN GPIOT_RXP11 GMII/MII transmit enable
ETH_TXD3 TXD[3] GPIOR_178 GMII and MII transmit data
ETH_TXD2 TXD[2] GPIOR_183 GMII and MII transmit data
ETH_TXD1 TXD[1] GPIOR_174 GMII and MII transmit data
ETH_TXD0 TXD[0] GPIOR_173 GMII and MII transmit data
ETH_RXC RXC GPIOL_73 GMII and MII receive clock
ETH_RXDV RXDV/AD[2] GPIOT_RXP12 GMII and MII receive data valid
ETH_RXD3 RXD[3]/AN[1] GPIOL_75 GMII and MII receive data
ETH_RXD2 RXD[2]/AN[0] GPIOL_17 GMII and MII receive data
ETH_RXD1 RXD[1]/TXDLY GPIOL_63 GMII and MII receive data
ETH_RXD0 RXD[0]/AD[3] GPIOL_62 GMII and MII receive data
ETH_RSTN RSTN GPIOT_RXN13 Global reset input; active-low to reset the
entire chip
ETH_MDC MDC GPIOT_RXN12 Serial clock line
ETH_MDIO MDIO GPIOT_RXP13 Serial data line
ETH_IRQ IRQ GPIOT_RXN11 Interrupt to MAC
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