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AGP Master 1 WS Write
Default: Disabled
This implements a single delay when writing to the AGP Bus. By default,
two-wait states are used by the system, allowing for greater stability.
AGP Master 1 WS Read
Default: Disabled
This implements a single delay when reading to the AGP Bus. By
default, two-wait states are used by the system, allowing for greater
stability.
After you have made your changes in the AGP & P2P Bridge Control
screen, press <Esc> to return to the Advanced Chipset Features screen.
CPU & PCI Bus Control
Scroll to CPU & PCI Bus Control and press <Enter> to view the
following screen:
CMOS Setup Utility – Copyright © 1984 – 2000 Award Software
CPU & PCI Bus Control
Item Help
CPU to PCI Write Buffer
Enabled
PCI Master 0 WS Write
Enabled
PCI Delay Transaction
Disabled
Menu Level
↑
↓
→
←
: Move Enter : Select
+/-/PU/PD:Value:
F10: Save ESC: Exit F1:General Help
F5:Previous Values
F6:Fail-Safe Defaults
F7:Optimized Defaults
CPU to PCI Write Buffer
Default: Enabled
When enabled, up to four words of data can be written to the PCI bus
without interrupting the CPU. When disabled, a write buffer is not used
and the CPU read cycle will not be completed until the PCI bus signals
that it is ready to receive the data.
PCI Master 0 WS Write
Default: Enabled
When set to Enabled, writes to the PCI bus are executed with zero wait
states.