ECS 945GCT-M3, Руководство пользователя, Страница: 40 / 60

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Using BIOS
Limit CPUID MaxVal (Disabled)
This item can support Prescott CPUs for old OS. Users please note that under NT
4.0, it must be set “Enabled”, while under WinXP, it must be set “Disabled”.
C1E Support (Enabled)
Use this item to decrease the bus ratio that reduces the consumption of CPU electric-
ity and power.
Execute Disable Bit (Disabled)
This item is a security feature that helps you protect your CPU and operating system
against malicious software executing code. This item is available when CPU supports
the feature.
Vanderpool Technology (Enabled)
This item enables or disables the Vanderpool Technology. When disabled, forces
the VT function will close.
Frequency Unlimit (Disabled)
This item enables or disables the over-clocking frequency.
Intel (R) SpeedStep (tm) Tech. (Enabled)
This item enables or disables the Intel (R) SpeedStep (tm) technology. When
enabled, allows enhance Intel SpeedStep Technology transitions.
Hard Disk Boot Priority (Press Enter)
Scroll to this item and press <Enter> to view the following screen:
TM2 Bus VID (0.8375V)
This item represents the voltage of the throttled performance state that will be
initiated
when the on-die sensor goes from not hot to hot.
1. Pri.Master:
2. Pri.Slave:
3. Sec. Master:
4. Sec. Slave:
5. USBHDD0:
6. USBHDD1:
7. USBHDD2:
8. Bootable Add-in Cards
Item Help
Menu Level
Phoenix-AwardBIOS CMOS Setup Utility
Hard Disk Boot Priority
Use < > or < >
to select a device, then
press <+> to move it
up, or <-> to move it
down the list. Press
<ESC> to exit this
menu.
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
CPU L1&L2 Cache (Enabled)
All processors that can be installed in this mainboard use internal level 1 (L1) and
external level 2 (L2) cache memory to improve performance. Leave this item at the
default value for better performance.
TM2 Bus Ratio (0X)
This item represents the frequency (bus ratio) of the throttled performance state
that will be initiated when the on-die sensor goes from not hot to hot).