Eclipse EC-11-xxx40, Руководство пользователя

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EC-11User’s Manual
03-32-00418-05 DALSA Corp.
EXRCLK
EXRCLK is an optional input signal used to control readout timing. EXRCLK is applied to
the read portion of a FIFO and directly drives STROBE and LVAL.
Data Clocking/Output Signals
Verify the presence of all data clocking and output signals. Trigger the oscilloscope from
the rising edge of LVAL (ch1; DC coupled). Adjust the oscilloscope time base to allow for
a complete cycle of each signal:
•
STROBE
—Verify the presence of the STROBE and STROBEB signals. There should be
a continuous clock signal present at the same frequency as your data rate. Sample data
on the rising edge of STROBE.
•
LVAL
—Verify the presence of the LVAL and LVALB signals.
•
Digital Output
—Do not probe LVDS data signals with a scope probe unless it has less
than 0.5pf of capacitance. If you can probe safely, use LVAL to trigger the scope
sweep. Illuminate the camera target and check each individual digital output signal on
ch2 of the oscilloscope (±D0 - D7 on the digital output connector). The digital output
data signal should change value when light is blocked from the camera lens. Ensure
that the bitpattern, that is output just before the active video pixels, is correct (as
specified in Chapter 2).
If any of the above signals are missing, contact DALSA product support.
4.2 Troubleshooting Using the Serial Interface
The following commands can aid in debugging. (The complete command protocol is
described in Appendix C and D.)
Verify Parameters
To verify the camera setup, send the
get_camera_parameters
command.
Verify Factory Calibrated Settings
To restore the camera’s factory settings and reset the FPN and PRNU coefficients to 0,
send the
restore_factory_settings
command.
After executing this command send the
get_camera_parameters
command to verify
the factory settings.
Verify Timing and Digital Video Path
To generate a test pattern, use the command
set_video_mode 2
. The test pattern is a
ramp from 0 to 255DN, then starts at 0 again. Use the test pattern to verify the proper
timing and connections between the camera and the frame grabber and verify the proper
output along the digital processing chain.