Dynamic Engineering PCIeBiSerialDb37-LM9 Скачать руководство пользователя страница 29 | Manualshive

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Dynamic Engineering PCIeBiSerialDb37-LM9 Скачать руководство пользователя страница 29

Embedded Solutions

Page 29

LM9_CHAN_TX

[0x1C] Channel Transmit Control Register (read/write)

Channel TX Control Register

Data Bit

Description

27-16

ClkDiv

15

TxMarkingBit

14

TxStartBit

13

TxClockSrc

12

TxClockDir

9

TxParitySel

8

TxRegPacket

7

TxClkPolarity

6

TxDataBitOrder

5

TxDataByteOrder

4

TxUnderFlowEn

3

TxAEIntEn

2

TxIntEn

1

spare

0

TxEn

Figure 17 PcieBiSerialDb37Lm9 Channel Transmit Control Register

TxEn when set causes the Transmit State Machine to begin operation. When the
Transmitter has determined that Data is in the Transmit FIFO, and a packet definition
has been read, and CTS is received, data will be transmitted. Clearing TxEn will return
the State Machine to the idle state, generally at the end of the current transmitted byte.

Disabling TxEn while transmitting is considered a “panic stop” situation. The FIFO’s
should be cleared and the process restarted from scratch when this is done. Restarting
without clearing will allow the data to be completed but with the incorrect remaining
packet count likely leading to error(s) being detected.

TxIntEn when set enables the transmitter to generate an interrupt for each packet sent.
When not enabled the status is still available to allow for polling situations.
TxPacketCompleted is the corresponding status bit.

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Содержание PCIeBiSerialDb37-LM9

Страница 1: ...A 95060 831 457 8891 Fax 831 457 4793 http www dyneng com sales dyneng com Est 1988 User Manual PCIeBiSerialDb37 LM9 ARC210 IF Parallel Port PCIe 4 lane Module Transmit and Receive Interface Protocols...

Страница 2: ...without notice Furthermore Dynamic Engineering assumes no liability arising out of the application or use of the device described herein The electronic equipment described herein generates uses and c...

Страница 3: ...CHAN_RX_FIFO_COUNT 27 LM9_CHAN_FIFO 27 LM9_CHAN_TX_AMT_LVL 28 LM9_CHAN_RX_AFL_LVL 28 LM9_CHAN_TX 29 LM9_CHAN_TX_PACKET_LEN_FIFO 31 LM9_CHAN_TX_PACKET_LEN_REG 32 LM9_CHAN_RX 33 LM9_CHAN_RX_PACKET_LEN_F...

Страница 4: ...Embedded Solutions Page 4 Out of Warranty Repairs 41 SPECIFICATIONS 42 ORDER INFORMATION 43...

Страница 5: ...IGURE 11 PCIEBISERIALDB37LM9 TX FIFO DATA COUNT PORT 26 FIGURE 12 PCIEBISERIALDB37LM9 READ DMA POINTER REGISTER 26 FIGURE 13 PCIEBISERIALDB37LM9 RX FIFO DATA COUNT PORT 27 FIGURE 14 PCIEBISERIALDB37LM...

Страница 6: ...nce The IO are buffered from the FPGA with differential transceivers The transceivers can be populated with LVDS or RS 485 compatible devices The power plane for the transceivers is isolated to allow...

Страница 7: ...r The ARC 210 interface is serial with an interface similar to a UART The Start and Marking bits have opposite polarity with the Start bit being active high 1 and the marking state being a 0 on the li...

Страница 8: ...synchronized Receive Data As the data is captured the marking state is checked to allow for initial start up 10 bits of marking bits in a row The state machines check if in the marking state and then...

Страница 9: ...as there is data in the FIFO Please note that the Data in the FIFO s are packed on a Packet basis The last LW is padded as necessary to reach 32 bits On the receive side the storage register is clear...

Страница 10: ...hierarchy The Dynamic Engineering Windows driver uses the hierarchical approach to allow for more consistent software with common bit maps and offsets This implentation has only one channel The channe...

Страница 11: ...can control the entire transfer Head to tail operation can also be programmed with two memory spaces with two interrupts per loop The hardware is organized with the IO function in channel 0 and the c...

Страница 12: ...ffset register data R W define LM9_BASE_GPIO_IO 0x004C 19 LM9Base GPIO Data IO offset read only Figure 3 PCIeBiSerialDb37LM9 Internal Address Map Base Functions The address map provided is for the loc...

Страница 13: ...ad port including pipeline define LM9_CHAN_FIFO 0x00000010 4 LM9Chan FIFO for single word RW define LM9_CHAN_TX_AMT_LVL 0x00000014 5 LM9Chan TX almost empty level RW define LM9_CHAN_RX_AFL_LVL 0x00000...

Страница 14: ...o the PLL The IO for the ARC 210 direction and termination are hardwired in this design The ports are unidirectional and initialization is simplified with this approach The GPIO ports can be programme...

Страница 15: ...he DMA transfer the Host will receive an interrupt The receiver can be stopped and the FIFO reset to clear out any extra data captured For on the fly processing multiple shorter DMA segments can be pr...

Страница 16: ...register is where the Sdata output value is specified or read back pll_s2 This is an additional control line to the PLL that can be used to select additional pre programmed frequencies Set to 0 for m...

Страница 17: ...ermine which PcieBiserialDb37Lm9 physical card matches each PCI address assigned in a system with multiple cards installed The DIPswitch can also be used for other purposes software revision etc The s...

Страница 18: ...al channels 0 Unmasked Ch0 Interrupt Figure 7 PcieBiSerialDb37Lm9 Status Port Bit Map Channel Interrupt The local interrupt status from the channel Each channel can have different interrupt sources DM...

Страница 19: ...pass 1 Receive FIFO Reset 0 Transmit FIFO Reset Figure 8 PcieBiSerialDb37Lm9 channel Control Register FIFO Transmitter Receiver Reset When set to a one the transmit and or receive FIFOs will be reset...

Страница 20: ...a higher priority over other lower rate channels ByPass when set allows the FIFO to be used in a loop back mode internal to the device A separate state machine is enabled when ByPass is set and the T...

Страница 21: ...t 15 Read DMA Interrupt Occurred 14 Write DMA Interrupt Occurred 13 Read DMA Error Occurred 12 Write DMA Error Occurred 11 RxAFLvlIntLat 10 TxAELvlIntLat 9 RxParityErrorLat 8 spare 7 spare 6 Rx FIFO F...

Страница 22: ...w error is declared Tx FIFO Empty When a one is read the FIFO contains no data when a zero is read there is at least one data word in the FIFO If the FIFO is empty when time to read transmitted data f...

Страница 23: ...le to clean up and return to the idle state If SW has cleared the start bit to terminate the data transfer SW can use the IDLE bit to determine when the HW has completed its task and returned Rx IDLE...

Страница 24: ...a write back with this bit set Tx Packet Completed Lat When a one is read the transmitter has transmitted at least one of the stored packets The signal is latched and can be cleared via write back wit...

Страница 25: ...of buffer memory blocks This process is continued until the end of chain bit in one of the next pointer values read indicates that it is the last chaining descriptor in the list All three values are o...

Страница 26: ...rt the DMA engine reads three successive long words beginning at that address Essentially this data acts like a chaining descriptor value pointing to the next value in the chain The first is the addre...

Страница 27: ...unt read only RX FIFO Data Count Port Data Bit Description 31 16 Spare 15 0 RX Data Words Stored Figure 13 PcieBiSerialDb37Lm9 RX FIFO data count Port This read only register port reports the number o...

Страница 28: ...ister is R W for 16 bits The mask is valid for a size matching the depth of the FIFO LM9_CHAN_RX_AFL_LVL 0x18 Rx almost full read write Rx Almost Full Level Register Data Bit Description 31 16 Spare 1...

Страница 29: ...smit FIFO and a packet definition has been read and CTS is received data will be transmitted Clearing TxEn will return the State Machine to the idle state generally at the end of the current transmitt...

Страница 30: ...sent D31 first D0 last Please note the start bit parity bit and stop marking states are not affected TxClkPolarity When set inverts the clock used by the transmitter The default 0 setting uses the ris...

Страница 31: ...encies below the PLL capability would be the exception In this case a 1 MHz or similar frequency can be programmed into the PLL and the divisor used to reach lower frequencies LM9_CHAN_TX_PACKET_LEN_F...

Страница 32: ...t Port Data Bit Description 31 0 TX Data Bytes per Packet Figure 19 PcieBiSerialDb37Lm9 TX Packet Size Register This read write register port holds the number of bytes to transmit per packet Data is r...

Страница 33: ...unted and the byte is stored Once synchronized the receiver requires 1 stop bit between words RxIntEn when set enables the RxPacketCompleted status to cause an interrupt to the host The status is set...

Страница 34: ...ault 0 setting uses the falling edge to sample the received data When set the rising edge is used RxParitySel is used to control whether odd or even parity is tested against the parity received on eac...

Страница 35: ...rom the FIFO LM9_CHAN_RX_TIMEOUT_LEN 0x3C RX TimeOut Length RX TimeOut Port Data Bit Description 31 0 Max Clocks before new Packet Figure 22 PcieBiSerialDb37Lm9 RX TimeOut Length This read write only...

Страница 36: ...used in several ways The length can be used to match the known packet size expected from the receiver The length can be used to create smaller SW defined packets with a received amorphous stream A lar...

Страница 37: ...ifferent set up The loop back plug is a DB37 connector with the interconnections protected with a connector shell Signal From To Signal GPIO_0 7 13 GPIO_6 GPIO_0 8 14 GPIO_6 GPIO_1 26 32 GPIO_7 GPIO_1...

Страница 38: ...PIO_0 7 8 IO_7p GPIO_1 IO_7m GPIO_1 26 27 IO_8p GPIO_2 IO_8m GPIO_2 9 10 IO_9p GPIO_3 IO_9m GPIO_3 27 29 IO_10p GPIO_4 IO_10m GPIO_4 11 12 IO_11p GPIO_5 IO_11m GPIO_5 30 31 IO_12p GPIO_6 IO_12m GPIO_6...

Страница 39: ...ng areas by powering the equipment together and by having a good ground reference Keep cables short Flat cables even with alternate ground lines are not suitable for long distances In addition series...

Страница 40: ...CIe is secured against the chassis with the connectors and front panel If more security against vibration is required a chassis with top side support can be used The PCIeBiSerialDb37 has a wider keep...

Страница 41: ...y the return Dynamic Engineering will not be responsible for damages due to improper packaging of returned items For service on Dynamic Engineering Products not purchased directly from Dynamic Enginee...

Страница 42: ...ad Back registers FIFO R W 32 bit boundaries Initialization Programming procedure documented in this manual Access Modes LW to registers read write to most registers Access Time Frame to TRDY 121 nS 4...

Страница 43: ...l Temp 40 85C Standard this design COM to change to commercial temp parts 0 70 Dbterm37 37 position terminal block with DB37 connector http www dyneng com DBterm37 html Dbcabl37 DB37 cable compatible...

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