Dynamic Engineering PCIeBiSerialDb37-LM9, Руководство пользователя

Страница: 10 / 43

Embedded Solutions Page 10
The registers are mapped as 32 bit words and support 32 bit access. Most registers are
read-writeable. The Windows® and Linux compatible drivers are available to provide
the system level interface for this version of the Biserial. Use standard C/C++ to control
your hardware or use the Hardware manual to make your own software interface. The
software manuals are also available on-line.
PcieBiserialDb37 can be used for multiple purposes with applications in
telecommunications, control, sensors, IO, test; anywhere multiple independent or
coordinated IO are useful.
PcieBiserialDb37 features a Xilinx FPGA, and high speed differential devices. The
FPGA contains the PCI interface and control required for the parallel interface.
The Xilinx design incorporates the “PCI Core” and additional modules for DMA in
parallel with a direct register decoded programming model. The design model has a
“base” level with the basic board level functions and “channels” which contain IO
oriented functions. In the LM9 design the ARC-210 functions are designed into the
channel and the PLL programming, switch, GPIO and other common or basic functions
are in the base design.
From a software perspective the design can be treated as “Flat” or as a hierarchy. The
Dynamic Engineering Windows® driver uses the hierarchical approach to allow for more
consistent software with common bit maps and offsets. This implentation has only one
channel. The channel function was kept to allow for future expansion with more than 1
ARC-210 interface or a secondary function in added channels. The user software can
control the Channels with the same calls and use the channel number to distinguish.
This makes for consistent and easier to implement user level software.
The hardware is designed with each of the channels on a common address map – each
channel has the same memory allocated to it and as much as possible the offsets within
each space are defined in the same way or similar way. Again this make understanding
each port easier to accomplish and less likely to have errors.
The transceivers are initialized to the receive state. Once a channel is defined via
software to be a transmitter the IO are enabled and driven to the appropriate levels.
Terminations are activated for ports defined to be receivers.
PcieBiserialDb37 is part of the PCIe Module family of modular I/O components. The
PcieBiserialDb37 conforms to the PCIe standard. This guarantees compatibility with
your PCIe system. The base is 4 lane operation. The design can handle 1-4 lanes
being available. LED’s are provided to show the active PCIe lanes.
Designs implemented on PC104p, PMC, IP and PCIe versions of the BiSerial family can