Embedded Solutions
Page 18
Specifications
Logic Interfaces:
PCIe up to 8 lanes per XMC Gen1 and Gen2 compliant switch and
clock buffer.
Access types:
PCIe TLP transactions. MSI interrupts.
CLK rates supported:
Gen1 and Gen2
Software Interface:
switch is auto configured and usually will not require any user
intervention.
Initialization:
switch selections for VPWR, bezel grounding, and cable options
Interface:
XMC front bezel via PCIe bracket and User IO connector via DIN or
SCSI connector or cross connection of XMC rear IO connectors.
Mix and match between External and Internal connections.
Dimensions:
full length PCIe board with offset PCI card guide support.
Construction:
High Temp FR4 Multi-Layer Printed Circuit, Through Hole and
Surface Mount Components.
