It
also operates
in
a
maximum mode so
a
coprocessor
can
be
added
as a
feature.
The
processor operate
in
two
modes
which
can
be switched, namely
the
Normal
mode
and the
Turbo mode. When
the processor
is
operating
in
Normal mode (4.77MHz), the
frequency
which
is
derived
from
a
14.318MHz crystal,
is
divided
by
three
for
the
pro—
cessor
clock,
and
by 4 to
obtain
the
3.58MH2 color burts
signal required for color television. When
the processor
is
operating
in
Turbo
mode
(10MHz),
the frequency
is
de-
rived from
30MHz.
,
DMA
Three
of
the
four
DMA
channels are
available on
the
l/O
bus and support high-speed
data
transfers between
l/O
devices and
memory without
processor
intervention.
The
fourth
DMA
channel
is
programmed
to
refresh
the system
dynamic memory. This
is
done
by
programming
a
channel
of
the timer counter device
to
request
periodically a
dummy
DMA
transfer.
This action
creates
a
memory-read
cycle which
is
available
to
refresh
dynamic
storage
both
on
the system board and expansion
slots.
All
DMA
data
transfers except the refresh channel take
five
processor
clocks
of
210ns
or 1.05us
if
the
processor
ready
line is not
deactivated. Refreshing
DMA
cycles
takes
four
clocks
(840ns).
Timer
The
three programmable timer/counters are used
by
the system
as
follows:
Channel
0 is
used
as a
general-
purpose
timer providing a
constant
time
base
for
implementing
a
time-of—day
clock;
Channel
1
is
used
to
time
and request refresh cycles
from
the
DMA
channel;
and Channel
2 is
used
to
support the tone generation
for
the
audio
speaker.
Each
channel has a
minimum timing
resolution
of
1.05us.
22
0
O
Interrupt
Of
the eight
prioritized
levels
of
interrupts,
six
are
bussed
to
the expansion slots
for
use
by
the interface
cards.
Two
levels
are used
on
the system
board.
Level 0,
the highest
priority,
is
attached
to
Channel
0 of
the
timer/counter and provides a periodic
interrupt for
the
time-of-day
clock. Level
1
is
attached
to
the keyboard
adapter
circuits
and receives
an interrupt for
each scan
code sent
by
the
keyboard. The
Non—Maskable
Interrupt
(NMI)
of
the
8088
is
used
to report memory-parity errors.
Memory
The
system
board
supports
both
ROM/EPROM and
FWV
memory.
It
has space
for 32KB
x
1
and
8KB
x
1
of ROM
or
EPROM. This
ROM
contains
a
power-on
self—test, l/O
drivers, dot
patterns
for 128
characters
in
graphics
mode
and a
diskette. The
system
board also
has
from
256KB to
640KB
of
RM
memory.
A
minimum
system has
256KB
of
memory.
Keyboard
The system board contains the
adapter
circuits for
attaching the serial interface
from
the keyboard. These
circuits
generate
an interrupt to
the processor when a
complete scan code
is
received. The interface can
request
execution
of
a diagnostic
test
in
the keyboard. The
keyboard interface
is
a
five-pin
DIN
connector
on
the
system board that extends
through
the rear panel
of
the
system
unit.
23
