Dolphin PXH822, Руководство пользователя

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PXH822 User’s Guide – Dolphin Interconnect Solutions Page 15
Technical Information
PCIe Cable Port Signals
The external PCI Express SFF-8644 cable connector supports the following signals:
•
PETpN/PETnN: PCI Express Transmitter pairs, labeled where N is the Lane number (starting with 0); “p” is the true signal
while “n” is the complement signal.
•
PERpN/PERnN: PCI Express Receiver pairs, labeled where N is the Lane number (starting with 0); “p” is the true signal
while “n” is the complement signal.
•
PWR: Power to support AOC and signal conditioning components within the cable assembly.
•
MGTPWR: Power supplied to the connector for cable management components that are needed while the link is not
active. This needs to be active if the subsystem has power.
•
CBLPRSNT#: Cable present detect, an active-low signal pulled-down by the cable when it is inserted into the PXH832
connector.
•
CADDR: Signal used to configure the upstream cable management device address.
•
CINT#: Signal asserted by the cable assembly to indicate a need for service via the CMI controller.
•
CMISDA: Management interface data line. Used for both initial link setup and sideband messages when used with CMI
compliant cables.
•
CMISCL: Management interface clock line. Used for both initial link setup and sideband messages when used with CMI
compliant cables.
External PCIe x4 Cable Connector Pin-Out
Column
Row 9 8 7 6 5 4 3 2 1
D GND PETn2 PETp2 GND PETn1 PETp1 GND MGTPWR PWR
C GND PETn3 PETp3 GND PETn0 PETp0 GND CMISDA CMISCL
B GND PERn2 PERp2 GND PERn1 PERp1 GND CBLPRSNT# PWR
A GND PERn3 PERp3 GND PERn0 PERp0 GND CINT# CADDR
Table 9; External PCIe x4 cable Pin-Out
PCIe Cable Port Mapping
The PXH832 card have a quad SFF-8644 connector. The ports are mapped as showed in the table below. The card utilized PCIe lane
reversal.
Table 10 : PCIe Cable Port Mapping
Cable Port x16 Dual x8 Quad x4 PCIe 3.0 Cable Pin
L15 L7 L3 TX0/RX0
L14 L6 L2 TX1/RX1
L13 L5 L1 TX2/RX2
L12 L4 L0 TX3/RX3
L11 L3 L3 TX0/RX0
L10 L2 L2 TX1/RX1
L9 L1 L1 TX2/RX2
L8 L0 L0 TX3/RX3
L7 L7 L3 TX0/RX0
L6 L6 L2 TX1/RX1
L5 L5 L1 TX2/RX2
L4 L4 L0 TX3/RX3
L3 L3 L3 TX0/RX0
L2 L2 L2 TX1/RX1
L1 L1 L1 TX2/RX2
L0 L0 L0 TX3/RX3
1
2
3
4