Diversified Technology CPB-4612, Руководство по настройке и обслуживанию

Страница: 15 / 106

4
1.2 Features
There are two SKU's of the cPB-4612. The first is the cPB-4612, which has a 64bit/66Mhz PMC site and a
32bit/33Mhz PMC site. . The second is the cPB-4612 w/ IDE, which has a 64bit/66Mhz PMC site and an
on-board 2.5” HDD IDE connector. Other features include:
•
CompactPCI Specification, PICMG 2.0, Version 2.1**
compliant
•
CompactPCI Specification, PICMG 2.16, Version 1.0**
compliant
• 6U single-slot CompactPCI form factor
•
Mobile Intel Pentium M, micro FCBGA package
•
Intel
®
855GME GMCH and 6300ESB ICH
•
Integrated Intel Extreme Graphics 2 controller
• Dual 10/100/1000 Mb/s Ethernet (both at the J3 backplane connector to support PICMG 2.16)
• 10/100 Mb/s Ethernet (available at the front panel)
•
1 MB of Level 2 cache
•
400 MHz front side bus
• Socketed 256 MB, 512 MB, 1 GB, or 2GB of DDR SDRAM memory at 200, 266, or 333 MHz
•
Dual stage watchdog timer
•
IPMI support
•
Option for either a single on-board PCI Mezzanine Card (PMC) slot (32-bit / 33MHz) or a primary IDE
channel that supports an on-board 2.5 inch hard disk
•
64bit / 66Mhz @ 3.3V PCI Mezzanine Card (PMC) slot
•
Two 16C550 RS-232 serial ports (COM1 available at the faceplate, COM2 available through the J5
backplane connector)
• Push Button Reset on the front panel
•
1 USB on front panel, 2 USB ports available via RTM
•
Rear-Panel I/O Availability (at J5) includes the following:
–
Secondary IDE channel
–
Serial ATA
–
Two USB ports
–
VGA video
–
Serial Port
• Support for Microsoft Windows 2000/XP, Red Hat Linux, and Solaris 8/9
•
Standard AT* Systems include:
– Two enhanced interrupt controllers (8259)
– Three counter/timers (one 8254)
– Real-time clock/CMOS RAM (146818B)
– Two enhanced DMA controllers (8237)
1.3 Functional Blocks
The following topics provide overviews of the cPB-4612's main features, some of which are shown in the
functional block diagram below.