Digital Voice Systems VC-20-PRJ25, Руководство пользователя

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VC-20-PRJ25 IMBE™ Vocoder Board
User’s Manual
Page 6
Section 3 – Technical Specifications
DVSI Confidential Proprietary
VC-20-PRJ25 Connector Signal Descriptions
DESLNCE The DESLNCE flag signals the decoder that silence has been detected during the
current frame. IF DESLNCE is active while FMDE is high, the decoder ignores the
current frame of channel data and mutes the output VFRO.
DINRS DINRS is a VC-20-PRJ25 reset signal. An active high level on DINRS for a duration
of at least 300ns will reset the VC-20-PRJ25. DINRS will generate RESX and
RESET. The VC-20-PRJ25 will pull this signal to its inactive state (low) when it is not
being driven by an external source (it may be left unconnected if not being used).
ENSLNCE The ENSLNCE flag is activated (low) by the encoder if it detects silence on VRXI.
The ENSLNCE flag is deactivated (high) by the encoder two frames prior to the onset
of voice activity. This is shown in figure 1. Note: silence detection is currently disabled,
consequently ENSLNCE is never active.
FMEN
Silence Voice Voice Voice Silence
ENSLNCE
Figure 1: Voice/Silence Detection Timing
FEC_OFF The FEC_OFF signal can be pulled low to disable all error correction and interleaving.
If FEC_OFF is pulled low, the prioritized bit vectors (88 bits) are output on ITXD and
QTXD durring the first 44 clock cycles of each 20 ms transmit frame, and ITXD and
QTXD are set to zero during the remaining 28 clock cycles of each transmit frame.
Also if FEC_OFF is pulled low, the prioritized bit vectors must be input on IRXD2-0
and QRXD2-0 during the first 44 clock cycles of each 20 ms receive frame, and
IRXd2-0 and IRXd2-0 are ignored during the remaining 28 clock cycles of each
receive frame. The FEC_OFF signal is sampled once every 20 ms when FMEN is
high. If left unconnected, this signal is pulled internally to its inactive state (high).
FMDE This is the decoder frame flag which identifies the frame boundary of the channel input
data. FMDE must be active for one clock period of RXCK every 20 ms.
FMEN This is the encoder frame flag which identifies the frame boundary of the channel output
data. FMEN must be active for one clock period of TXCK every 20 ms.