ZYBO™ FPGA Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
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Voltage regulator circuits from Analog Devices create the required 3.3V, 1.8V, 1.5V, and 1.0V supplies from the main power input.
Table 2 provides additional information (typical currents depend strongly on FPGA configuration and the values
provided are typical of medium size/speed designs).
Supply
Circuits
Device
Current (max/typical)
3.3V
FPGA I/O, USB ports, Clocks,
Ethernet, SD slot, Flash, HDMI
IC26#1: ADP5052
2.5A/0.1A to 1.5A
1.0V
FPGA, Ethernet Core
IC26#2: ADP5052
2.5A/0.2A to 2.1A
1.5V
DDR3
IC26#3: ADP5052
1.2A/0.1A to 1.2A
1.8V
FPGA Auxiliary, Ethernet I/O,
USB OTG
IC26#4: ADP5052
1.2A/0.1A to 0.6A
1.8V
XADC Analog
IC26#5: ADP5052
200mA/20mA
3.3V
Audio Analog
IC6: ADP150
150mA/50mA
1.25V
XADC Precision Reference
IC27: ADR127
5mA/50uA
Table 2. ZYBO power supplies.
The supply rails are daisy-chained to follow the Xilinx-recommended start-up sequence. Flicking the power switch
(SW4) will enable the 1.0V rail, which enables the 1.8V digital supply rail, which in turn enables the I/O supply rails
3.3V and 1.5V. The 1.25V reference and 1.8V analog supply ramp together with the 3.3V rail. Once all the channels
of the ADP5052 (IC26) supply reach regulation, the PGOOD signal will assert, enabling the 3.3V audio supply,
lighting up the power LED (LD11), and de-asserting the Power-On Reset signal (PS_POR_B) of the Zynq.
Each power supply uses a soft-start ramp of 1-10ms to limit in-rush current. There is an additional delay of at least
130ms after the power rails reach regulation and before the Power-On Reset signal de-assert to allow for the
PS_CLK (IC22) to stabilize.
2
Zynq AP SoC Architecture
The Zynq AP SoC is divided into two distinct subsystems: The Processing System (PS), and the Programmable Logic
(PL). Figure 3 shows an overview of the Zynq AP SoC architecture, with the PS colored light green and the PL in
yellow. Note that the PCIe Gen2 controller and Multi-gigabit transceivers are not available on the Zynq-7010
device.
