ZYBO™ FPGA Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
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through it line by line using Xilinx SDK. The ZYBO Base System Design includes a tutorial for debugging software
over JTAG in Xilinx SDK.
It is also possible to directly configure the PL over JTAG, independent of the processor. This can be done using
iMPACT or the Vivado Hardware Server.
The ZYBO is configured to boot in Cascaded JTAG mode, which allows the PS to be accessed via the same JTAG port
as the PL. It is also possible to boot the ZYBO in Independent JTAG mode by loading a jumper in JP6 and shorting it.
This will cause the PS to not be accessible from the onboard JTAG circuitry, and only the PL will be visible in the
scan chain. To access the PS over JTAG while in independent JTAG mode, users will have to route the signals for the
PJTAG peripheral over EMIO, and use an external device to communicate with it.
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SPI Flash
The ZYBO features a 4-bit SPI (quad-SPI) serial NOR flash. The Spansion S25FL128S is used on this board. The Multi-
I/O SPI Flash memory is used to provide non-volatile code and data storage. It can be used to initialize the PS
subsystem as well as configure the PL subsystem (bitstream). Spansion provides Spansion Flash File System (FFS)
for use after booting the Zynq-7000 AP SoC.
The relevant device attributes are:
128Mbit
x1, x2, and x4 support
Speeds up to 104 MHz, supporting Zynq configuration rates @ 100 MHz. In Quad-SPI mode, this
translates to 400Mbs
Powered from 3.3V
The SPI Flash connects to the Zynq-7000 AP SoC supporting up to Quad-I/O SPI interface. This requires connection
to specific pins in MIO Bank 0/500, specifically MIO[1:6,8] as outlined in the Zynq datasheet. Quad-SPI feedback
mode is used, thus qspi_sclk_fb_out/MIO[8] is left to freely toggle and is connected only to a 20K pull-up resistor
to 3.3V. This allows a QSPI clock frequency greater than FQSPICLK2.
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DDR Memory
The ZYBO includes two Micron MT41J128M16JT-125 or MT41K128M16JT-125 DDR3 memory components creating
a single rank, 32-bit wide interface and a total of 512MiB of capacity. The DDR3 is connected to the hard memory
controller in the Processor Subsystem (PS), as outlined in the Zynq documentation. The PS incorporates an AXI
memory port interface, a DDR controller, the associated PHY, and a dedicated I/O bank. DDR3 memory interface
speeds up to 533 MHz/1066 Mbps are supported
1
.
The DDR3 uses 1.5V SSTL-compatible inputs. The two components are organized in a tree topology with a series
termination scheme while keeping traces as short as possible and matched.
ZYBO was routed with 40 ohm (+/-10%) trace impedance for single-ended signals, and differential clock and
strobes set to 80 ohms (+/-10%). A feature called DCI (Digitally Controlled Impedance) is used to match the drive
1
Maximum actual clock frequency is 525 MHz due to PLL limitation.
