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ZYBO™ FPGA Board Reference Manual 

 

 

Copyright Digilent, Inc. All rights reserved. 

Other product and company names mentioned may be trademarks of their respective owners.

 

Page 

22

 of 

26

 

 

Zynq

V16

Y16

P16

BTN3

BTN2

BTN1

3.3V

LEDs

Slide 
Switches

3.3V

Buttons

R18

BTN0

T16

W13

P15

G15

SW1

SW3

SW2

SW0

LD3

LD2

LD1

LD0

D18

G14

M15
M14

PL

PS

MIO51

BTN5

MIO50

BTN4

LD12

MIO7

3.3V

MIO 
Buttons

MIO 
LED

 

Figure 14. ZYBO GPIO. 

The high-efficiency LEDs are anode-connected to the Zynq via 330-ohm resistors, so they will turn on when a logic 
high voltage is applied to their respective I/O pin. Additional LEDs that are not user-accessible indicate power-on, 
FPGA programming status, and USB and Ethernet port status. 

The LED and two pushbuttons attached directly to the PS are accessed using the Zynq GPIO controller. This core is 
described in full in Chapter 14 of the Zynq Technical Reference Manual.  

 

14  Audio 

An Analog Devices SSM2603 Audio Codec provides integrated digital audio processing to the Zynq-7000 AP SoC. It 
allows for stereo record and playback at sample rates from 8 kHz to 96 kHz. 

On the analog side, the codec connects to three 3.5 mm standard audio jacks. There are two inputs: a mono 
microphone and a stereo line in. There is one stereo output, the headphone jack. Analog power is provided by a 
dedicated linear power supply (IC6). 

Audio Jack

 

Description

 

Channels 

Color

 

SSM2603 pin

 

J5 

Headphone Out 

Stereo 

Black 

L/RHPOUT 

J6 

Microphone In 

Mono 

Pink 

MICIN, MICBIAS 

J7 

Line In 

Stereo 

Light Blue 

L/RLINEIN 

 

Table 7. Analog audio signals. 

Содержание ZYBO

Страница 1: ...he rich set of multimedia and connectivity peripherals available on the ZYBO the Zynq Z 7010 can host a whole system design The on board memories video and audio I O dual role USB Ethernet and SD slot...

Страница 2: ...ed The ZYBO is compatible with Xilinx s new high performance Vivado Design Suite as well as the ISE EDK toolset These toolsets meld FPGA logic design with embedded ARM software development into an eas...

Страница 3: ...O LED 18 Logic Configuration Done LED 5 MIO Pushbuttons 2 19 Board Power Good LED 6 MIO Pmod 20 JTAG Port for optional external cable 7 USB OTG Connectors 21 Programming Mode Jumper 8 Logic LEDs 4 22...

Страница 4: ...is limit varies a lot between manufacturers and depends on many factors When in current limit once the voltage rails dip below their nominal value the Zynq is reset by the Power on Reset signal and po...

Страница 5: ...ply rails are daisy chained to follow the Xilinx recommended start up sequence Flicking the power switch SW4 will enable the 1 0V rail which enables the 1 8V digital supply rail which in turn enables...

Страница 6: ...itecture AMBA Interconnect DDR3 Memory controller and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins called MultiplexedI O or MIO pins Peripheral control...

Страница 7: ...on refer to the Zynq Technical Reference Manual available at www xilinx com Figure 3 depicts the external components connected to the MIO pins of the ZYBO The Zynq Board Definition File found on the D...

Страница 8: ...IO 501 1 8V Peripherals Pin ENET 0 USB 0 SDIO 0 UART 1 GPIO 16 TXCK 17 TXD0 18 TXD1 19 TXD2 20 TXD3 21 TXCTL 22 RXCK 23 RXD0 24 RXD1 25 RXD2 26 RXD3 27 RXCTL 28 DATA4 29 DIR 30 STP 31 NXT 32 DATA0 33...

Страница 9: ...of non volatile memory specified by the mode register to the 256 KB of internal RAM within the APU called On Chip Memory or OCM The FSBL must be wrapped up in a Zynq Boot Image in order for the BootR...

Страница 10: ...lect it using JP7 6 Place a single jumper on JP5 shorting the two leftmost pins labeled SD 7 Turn the board on The board will now boot the image on the microSD card 3 2 QSPI Boot Mode The ZYBO has an...

Страница 11: ...oting the Zynq 7000 AP SoC The relevant device attributes are 128Mbit x1 x2 and x4 support Speeds up to 104 MHz supporting Zynq configuration rates 100 MHz In Quad SPI mode this translates to 400Mbs P...

Страница 12: ...ss variations and thermal drift Optimum starting values for the training process are the board delays propagation delays for certain memory signals Board delays are specified for each of the byte grou...

Страница 13: ...ith a single Micro USB cable 7 MicroSD Slot The ZYBO provides a microSD slot J4 for non volatile external memory storage as well as booting the Zynq The slot is wired to Bank 1 501 MIO 40 47 including...

Страница 14: ...ect to a USB host device and JP1 should not be shorted When acting as an embedded host the USB A connector J10 should be used to connect to a USB peripheral device and JP1 should be shorted The ZYBO s...

Страница 15: ..._CLK ACT LED LD7 LINK LED LD6 LED0 PHY_AD0 LED1 PHY_AD1 Figure 7 Ethernet PHY signals Two status indicator LEDs are on board near the RJ 45 connector that indicate traffic LD7 and valid link state LD6...

Страница 16: ...sed from the PS over EMIO as well The device address of the EEPROM is 1010000b For more information on using the Gigabit Ethernet MAC refer to the Xilinx Zynq TRM ug585 10 HDMI Source Sink Port An inp...

Страница 17: ...d uses 18 programmable logic pins to create an analog VGA output port This translates to 16 bit color depth and two standard sync signals HS Horizontal Sync and VS Vertical Sync The digital to analog...

Страница 18: ...lection control R G B signals to guns Cathode ray tube Cathode ray VGA cable Figure 9 Color CRT display Electron beams emanate from electron guns which are finely pointed heated cathodes placed in clo...

Страница 19: ...the cathode makes over the display area and a number of columns that corresponds to an area on each row that is assigned to one picture element or pixel Typical displays use from 240 to 1200 rows and...

Страница 20: ...tical Sync 32 us 25 6 us 3 84 us 640 ns 1 92 us 800 640 96 16 48 Clks Horiz Sync Time Figure 11 Signal timings for a 640 pixel by 480 row display using a 25MHz pixel clock and 60Hz vertical refresh A...

Страница 21: ...nal reference clock can be used as an input to the MMCMs and PLLs For a full description of the capabilities of the Zynq PL clocking resources refer to the 7 Series FPGAs Clocking Resources User Guide...

Страница 22: ...and USB and Ethernet port status The LED and two pushbuttons attached directly to the PS are accessed using the Zynq GPIO controller This core is described in full in Chapter 14 of the Zynq Technical...

Страница 23: ...ire a master clock of 12 288 Mhz resulting in a 48 kHz sampling rate For other frequencies and their respective configuration parameters consult the SSM2603 datasheet The codec has two modes master an...

Страница 24: ...es DONE to be de asserted The PL will remain unconfigured until it is reprogrammed by the processor or via JTAG 15 3 Processor Subsystem Reset The external system reset labeled PS_SRST BTN7 resets the...

Страница 25: ...the user accidently drives a signal that is supposed to be used as an input The downside to this added protection is that these resistors can limit the maximum switching speed of the data signals If...

Страница 26: ...on on using the XADC core refer to the Xilinx document titled 7 Series FPGAs and Zynq 7000 All Programmable SoC XADC Dual 12 Bit 1 MSPS Analog to Digital Converter It is also possible to access the XA...

Страница 27: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Digilent 410 279P KIT 410 279...

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