Digilent Nexys2 Скачать руководство пользователя страница 3

Nexys2 Reference Manual 

 

Digilent 

www.digilentinc.com 

 

Copyright Digilent, Inc. 

  Page 3/17 

                                  Doc: 502-134 

 

more than 100mA will be drawn through the USB cable (as required by the USB specification). A USB 
host can supply only 500mA of current at 5VDC. When using USB power, care must be taken to 
ensure the Nexys2 board and any attached peripheral boards do not draw more than 500mA, or 
damage to the host may result. The Nexys2 board typically consumes about 300mA of USB current, 
leaving about 200mA for peripheral boards. If peripheral boards require more current than the USB 
cable can supply, an external power supply should be used.  
 
The Nexys2 board uses a six layer PCB, with the inner layers dedicated to VCC and GND planes. 
The FPGA and the other ICs on the board all have a large complement of bypass capacitors placed 
as close as possible to each VCC pin. The power supply routing and bypass capacitors result in a 
very clean, stable, and low-noise power supply. 
 
 

FPGA and Platform Flash Configuration 

 
The FPGA on the Nexys2 board must be configured (or programmed) by the user before it can 
perform any functions. During configuration, a “bit” file is transferred into memory cells within the 
FPGA to define the logical functions and circuit interconnects. The free ISE/WebPack CAD software 
from Xilinx can be used to create bit files from VHDL, Verilog, or schematic-based source files. 
 
The FPGA can be programmed in two ways: 
directly from a PC using the on-board USB port, 
and from an on-board Platform Flash ROM (the 
Flash ROM is also user-programmable via the 
USB port). A jumper on the Nexys2 board 
determines which source (PC or ROM) the 
FPGA will use to load its configuration. The 
FPGA will automatically load a configuration 
from the Platform Flash ROM at power-on if the 
configuration Mode jumper is set to “Master 
serial”. If the Mode jumper is set to “JTAG”, the 
FPGA will await programming from the PC (via 
the USB cable). 
 
Digilent’s freely available PC-based Adept 
software can be used to configure the FPGA 
and Platform Flash with any suitable file stored 
on the computer. Adept uses the USB cable to 
transfer a selected bit file from the PC to the FPGA or Platform Flash ROM. After the FPGA is 
configured, it will remain so until it is reset by a power-cycle event or by the FPGA reset button 
(BTNR) being pressed. The Platform Flash ROM will retain a bit file until it is reprogrammed, 
regardless of power-cycle events. 
 
To program the Nexys2 board using Adept, attach the USB cable to the board (if USB power will not 
be used, attach a suitable power supply to the power jack or battery connector on the board, and set 
the power switch to “wall” or “bat”). Start the Adept software, and wait for the FPGA and the Platform 
Flash ROM to be recognized. Use the browse function to associate the desired .bit file with the FPGA, 
and/or the desired .mcs file with the Platform Flash ROM. Right-click on the device to be 
programmed, and select the “program” function. The configuration file will be sent to the FPGA or 
Platform Flash, and the software will indicate whether programming was successful. The configuration 

XCF02

Platform

Flash 

JTAG

header

JTAG

PROG

DONE

Vdd

Done

LED

FPGA

Reset

Button

(BTNR)

Spartan 3E

FPGA

Mode

Jumper

USB miniB

connector

Cypress
EZ-USB

Slave

serial

port

JTAG

port

 

Figure 4: Nexys2 programming circuits 

Содержание Nexys2

Страница 1: ...nd a host of sensor and actuator interfaces All user accessible signals on the Nexys2 board are ESD and short circuit protected ensuring a long operating life in any environment The Nexys2 board is fu...

Страница 2: ...ply and 100mA from the 3 3V supply Required current will increase if larger circuits are configured in the FPGA and if peripheral boards are attached The table above summarizes the power supply parame...

Страница 3: ...e USB port A jumper on the Nexys2 board determines which source PC or ROM the FPGA will use to load its configuration The FPGA will automatically load a configuration from the Platform Flash ROM at po...

Страница 4: ...udes a 50MHz oscillator and a socket for a second oscillator Clock signals from the oscillators connect to global clock input pins on the FPGA so they can drive the clock synthesizer blocks available...

Страница 5: ...rent A ninth LED is provided as a power on LED and a tenth LED indicates FPGA programming status Note that LEDs 4 7 have different pin assignments due to pinout differences between the 500 and the 120...

Страница 6: ...ter of the time but because the eye cannot perceive the darkening of a digit before it is illuminated again the digit appears continuously illuminated If the update or refresh rate is slowed to around...

Страница 7: ...s 500mA and then activates a transistor switch to connect the USB cable voltage to the main input power bus The Nexys2 board typically draws around 300mA from the USB cable and care should be taken es...

Страница 8: ...scan code When an extended key is released an E0 F0 key up code is sent followed by the scan code Scan codes for most keys are shown in the figure A host device can also send data to the keyboard Belo...

Страница 9: ...period is 20 to 30KHz The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field and moving to the left generates a negative numbe...

Страница 10: ...precise information or for information on other VGA frequencies refer to documentation available at the VESA website CRT based VGA displays use amplitude modulated moving electron beams or cathode ra...

Страница 11: ...to right and top to bottom and not during the time the beam is reset back to the left or top edge of the display Much of the potential display time is therefore lost in blanking periods when the beam...

Страница 12: ...erived Timings for sync pulse width and front and back porch intervals porch intervals are the pre and post sync pulse times during which information cannot be displayed are based on observations take...

Страница 13: ...tatic DRAM device organized as 8Mbytes x 16bits It can operate as a typical asynchronous SRAM with read and write cycle times of 70ns or as a synchronous memory with an 80MHz bus When operated as an a...

Страница 14: ...plete information is available for both devices from the manufacturer websites Table 2 Memory Address and Data Bus Pin Assignments Address signals Data signals ADDR0 NA ADDR8 H6 ADDR16 M5 DATA0 L1 DAT...

Страница 15: ...nectors are labeled JA nearest the power jack JB JC and JD nearest the expansion connector Pinouts for the Pmod connectors are provided in the table below More than 30 low cost are available for attac...

Страница 16: ...e FX2 Connector Pin Assignments J1A Name FPGA J1B Name FPGA 1 VCC3V3 1 SHIELD 2 VCC3V3 2 GND 3 TMS D15 3 TDO ROM 4 JTSEL 4 TCK A17 5 TDO FX2 5 GND 6 FX2 IO1 B4 6 GND 7 FX2 IO2 A4 7 GND 8 FX2 IO3 C3 8...

Страница 17: ...e FAIL After the memory test the buttons and switches will drive the LEDs and seven segment display so that all user I O devices can be manually checked If the self test is not resident in the Platfor...

Страница 18: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Digilent 410 134P KIT...

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