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Digilent Nexys2, Справочное руководство

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Nexys2 Reference Manual 

 

Digilent 

www.digilentinc.com 

 

Copyright Digilent, Inc. 

  Page 14/17 

                                  Doc: 502-134 

 

 
VDHL source code is available in a reference design posted on the Digilent website to illustrate the 
use of these devices. A base system builder file is also available for using these devices with Xilinx’s 
EDK tool and MicroBlaze processor core, both available from Xilinx. Complete information is available 
for both devices from the manufacturer websites. 

 
 
 

Table 2: Memory Address and Data Bus Pin Assignments

 

Address signals 

Data signals 

ADDR0:  NA 

ADDR8:  H6 

ADDR16:  M5 

DATA0:  L1 

DATA8:  L3 

ADDR1:  J1 

ADDR9:  F1 

ADDR17:  E2 

DATA1:  L4 

DATA9:  L5 

ADDR2:  J2 

ADDR10:  G3 

ADDR18:  C2 

DATA2:  L6 

DATA10:  M3 

ADDR3:  H4 

ADDR11:  G6 

ADDR19:  C1 

DATA3:  M4 

DATA11:  M6 

ADDR4:  H1 

ADDR12:  G5 

ADDR20:  D2 

DATA4:  N5 

DATA12:  L2 

ADDR5:  H2 

ADDR13:  G4 

ADDR21:  K3 

DATA5:  P1 

DATA13:  N4 

ADDR6:  J5 

ADDR14:  F2 

ADDR22:  D1 

DATA6:  P2 

DATA14:  R3 

ADDR7:  H3 

ADDR15:  E1 

ADDR23:  K6 

DATA7:  R2 

DATA15:  T1 

 
 

 
 
 
 
  
  

 

 

Figure 22: Nexys2 memory circuits 

Содержание Nexys2

Страница 1: ...nd a host of sensor and actuator interfaces All user accessible signals on the Nexys2 board are ESD and short circuit protected ensuring a long operating life in any environment The Nexys2 board is fu...

Страница 2: ...ply and 100mA from the 3 3V supply Required current will increase if larger circuits are configured in the FPGA and if peripheral boards are attached The table above summarizes the power supply parame...

Страница 3: ...e USB port A jumper on the Nexys2 board determines which source PC or ROM the FPGA will use to load its configuration The FPGA will automatically load a configuration from the Platform Flash ROM at po...

Страница 4: ...udes a 50MHz oscillator and a socket for a second oscillator Clock signals from the oscillators connect to global clock input pins on the FPGA so they can drive the clock synthesizer blocks available...

Страница 5: ...rent A ninth LED is provided as a power on LED and a tenth LED indicates FPGA programming status Note that LEDs 4 7 have different pin assignments due to pinout differences between the 500 and the 120...

Страница 6: ...ter of the time but because the eye cannot perceive the darkening of a digit before it is illuminated again the digit appears continuously illuminated If the update or refresh rate is slowed to around...

Страница 7: ...s 500mA and then activates a transistor switch to connect the USB cable voltage to the main input power bus The Nexys2 board typically draws around 300mA from the USB cable and care should be taken es...

Страница 8: ...scan code When an extended key is released an E0 F0 key up code is sent followed by the scan code Scan codes for most keys are shown in the figure A host device can also send data to the keyboard Belo...

Страница 9: ...period is 20 to 30KHz The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field and moving to the left generates a negative numbe...

Страница 10: ...precise information or for information on other VGA frequencies refer to documentation available at the VESA website CRT based VGA displays use amplitude modulated moving electron beams or cathode ra...

Страница 11: ...to right and top to bottom and not during the time the beam is reset back to the left or top edge of the display Much of the potential display time is therefore lost in blanking periods when the beam...

Страница 12: ...erived Timings for sync pulse width and front and back porch intervals porch intervals are the pre and post sync pulse times during which information cannot be displayed are based on observations take...

Страница 13: ...tatic DRAM device organized as 8Mbytes x 16bits It can operate as a typical asynchronous SRAM with read and write cycle times of 70ns or as a synchronous memory with an 80MHz bus When operated as an a...

Страница 14: ...plete information is available for both devices from the manufacturer websites Table 2 Memory Address and Data Bus Pin Assignments Address signals Data signals ADDR0 NA ADDR8 H6 ADDR16 M5 DATA0 L1 DAT...

Страница 15: ...nectors are labeled JA nearest the power jack JB JC and JD nearest the expansion connector Pinouts for the Pmod connectors are provided in the table below More than 30 low cost are available for attac...

Страница 16: ...e FX2 Connector Pin Assignments J1A Name FPGA J1B Name FPGA 1 VCC3V3 1 SHIELD 2 VCC3V3 2 GND 3 TMS D15 3 TDO ROM 4 JTSEL 4 TCK A17 5 TDO FX2 5 GND 6 FX2 IO1 B4 6 GND 7 FX2 IO2 A4 7 GND 8 FX2 IO3 C3 8...

Страница 17: ...e FAIL After the memory test the buttons and switches will drive the LEDs and seven segment display so that all user I O devices can be manually checked If the self test is not resident in the Platfor...

Страница 18: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Digilent 410 134P KIT...

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