Digilent Arty Z7 Скачать руководство пользователя страница 6

 

Arty Z7 Reference Manual  

Transfer Multisort Elektronik  / tme.eu  

An external power supply (e.g. wall wart) can be used by plugging it into the power jack (J18) 
and setting jumper JP5 to “REG”. The supply must use a coax, center-positive 2.1mm 
internal-diameter plug, and deliver 7VDC to 15VDC. Suitable supplies can be purchased from 
the Digilent website or through catalog vendors like DigiKey. Power supply voltages above 
15VDC might cause permanent damage. A suitable external power supply is included with 
the Arty Z7 accessory kit.  

Similar to using an external power supply, a battery can be used to power the Arty Z7 by 
attaching it to the shield connector and setting jumper JP5 to “REG”. The positive terminal of 
the battery must be connected to the pin labeled “VIN” on J7, and the negative terminal must 
be connected to the pin labeled GND on J7.  

The on-board Texas Instruments TPS65400 PMU creates the required 3.3V, 1.8V, 1.5V, and 
1.0V supplies from the main power input. Table 1.1 provides additional information (typical 
currents depend strongly on Zynq configuration and the values provided are typical of 
medium size/speed designs).  

The Arty Z7 does not have a power switch, so when a power source is connected and selected 
with JP5 it will always be powered on. To reset the Zynq without disconnecting and 
reconnecting the power supply, the red SRST button can be used. The power indicator LED 
(LD13) is on when all the supply rails reach their nominal voltage.  

 

Supply

  

Circuits

  

Current 
(max/typical)

  

3.3V  

FPGA I/O, USB ports, Clocks, Ethernet, SD slot, Flash, 
HDMI  

1.6A/0.1A to 1.5A  

1.0V   FPGA, Ethernet Core  

2.6A/0.2A to 2.1A  

1.5V   DDR3  

1.8A/0.1A to 1.2A  

1.8V   FPGA Auxiliary, Ethernet I/O, USB Controller  

1.8A/0.1A to 0.6A  

Table 1.1. Arty Z7 power supplies.

  

 

 
 

2 Zynq APSoC Architecture 

The Zynq APSoC is divided into two distinct subsystems: The Processing System (PS) and 
the Programmable Logic (PL). Figure 2.1 shows an overview of the Zynq APSoC 
architecture, with the PS colored light green and the PL in yellow. Note that the PCIe Gen2 
controller and Multi-gigabit transceivers are not available on the Zynq-7020 or Zynq-7010 
devices.  

Содержание Arty Z7

Страница 1: ...a unique set of software defined peripherals and controllers tailored by you for the target application The Vivado Petalinux and SDSoC toolsets each provide an approachable path between defining your...

Страница 2: ...Arty Z7 Reference Manual Transfer Multisort Elektronik tme eu 2...

Страница 3: ...sh with factory programmed 48 bit globally unique EUI 48 64 compatible identifier o microSD slot Power o Powered from USB or any 7V 15V external power source USB and Ethernet o Gigabit Ethernet PHY o...

Страница 4: ...s Look up Tables LUTs 17 600 53 200 Flip Flops 35 200 106 400 Block RAM 270 KB 630 KB Clock Management Tiles 2 4 Available Shield I O 26 49 On the Arty Z7 10 the inner row of the digital shield IO26 I...

Страница 5: ...t will be releasing a Video capable platform with Linux support in time for the SDSoC 2017 1 release Note that due to the smaller FPGA in the Arty Z7 10 only very basic video processing demos are incl...

Страница 6: ...wer input Table 1 1 provides additional information typical currents depend strongly on Zynq configuration and the values provided are typical of medium size speed designs The Arty Z7 does not have a...

Страница 7: ...rious peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins called Multiplexed I O or MIO pins Peripheral controllers that do not have their inputs and outputs connecte...

Страница 8: ...The Zynq Presets File found on the Arty Z7 Resource Center can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals MIO 500 3 3 V Peripherals Pin ENET 0...

Страница 9: ...A devices APSoC devices such as the Zynq 7020 are designed around the processor which acts as a master to the programmable logic fabric and all other on chip peripherals in the processing system This...

Страница 10: ...s hand off execution to the FSBL in OCM Stage 1 During this stage the FSBL first finishes configuring the PS components such as the DDR memory controller Then if a bitstream is present in the Zynq Boo...

Страница 11: ...shorting the two top pins labeled SD 7 Turn the board on The board will now boot the image on the microSD card 3 2 Quad SPI Boot Mode The Arty Z7 has an onboard 16MB Quad SPI Flash that the Zynq can...

Страница 12: ...ze the PS subsystem as well as configure the PL subsystem The relevant device attributes are 16 MB x1 x2 and x4 support Bus speeds up to 104 MHz supporting Zynq configuration rates 100 MHz In Quad SPI...

Страница 13: ...correct parameters For best DDR3 performance DRAM training is enabled for write leveling read gate and read data eye options in the PS Configuration Tool in Xilinx tools Training is done dynamically b...

Страница 14: ...be programmed communicated with via UART and powered from a computer attached with a single Micro USB cable The DTR signal from the UART controller on the FT2232HQ is connected to MIO12 of the Zynq d...

Страница 15: ...p USB3320 USB 2 0 Transceiver Chip with an 8 bit ULPI interface is used as the PHY The PHY features a complete HS USB Physical Front End supporting speeds of up to 480Mbs The PHY is connected to MIO B...

Страница 16: ...urpose then the Arty Z7 should be powered via a battery or wall adapter capable of providing more power such as the one included in the Arty Z7 accessory kit 9 Ethernet PHY The Arty Z7 uses a Realtek...

Страница 17: ...he MDIO bus is available for management The RTL8211E VL is assigned the 5 bit address 00001 on the MDIO bus With simple register read and write commands status information can be read out or configura...

Страница 18: ...V signal capable of delivering up to 50mA and one reserved RES pin All non power signals are wired to the Zynq PL with the exception of RES Pin Signal J11 source J10 sink Description FPGA pin Descript...

Страница 19: ...ng a common CEC wire Refer to the CEC addendum of HDMI 1 3 or later specifications for more information 11 Clock Sources The Arty Z7 provides a 50 MHz clock to the Zynq PS_CLK input which is used to g...

Страница 20: ...ttons and 4 individual LEDs as shown in Figure 12 1 The push buttons and slide switches are connected to the Zynq PL via series resistors to prevent damage from inadvertent short circuits a short circ...

Страница 21: ...steady logic 1 will result in the LED being illuminated at an uncomfortably bright level You can avoid this by ensuring that none of the tri color signals are driven with more than a 50 duty cycle Us...

Страница 22: ...UD_SD is used to mute the audio output It is connected to Zynq PL pin T17 To use the audio output this signal must be driven to logic high The frequency response of SK Butterworth Low Pass Filter is s...

Страница 23: ...tegrated to define an analog voltage The low pass filter 3dB frequency should be an order of magnitude lower than the PWM frequency so that signal energy at the PWM frequency is filtered from the sign...

Страница 24: ..._RST signal to toggle in order to trigger a reset on any attached shields 15 Pmod Ports Pmod ports are 2 6 right angle 100 mil spaced female connectors that mate with standard 2 6 pin headers Each 12...

Страница 25: ...Pmods have 0 ohm shunts instead of protection resistors the operator must take precaution to ensure that they do not cause any shorts 16 Arduino chipKIT Shield Connector The Arty Z7 can be connected t...

Страница 26: ...Shield Digital I O SCL I2C Clock See Section titled Shield Digital I O SDA I2C Data See Section titled Shield Digital I O SCLK SPI Clock See Section titled Shield Digital I O MOSI SPI Data out See Se...

Страница 27: ...e external power supply connector J18 Table 16 1 Shield Pin Descriptions 16 1 Shield Digital I O The pins connected directly to the Zynq PL can be used as general purpose inputs or outputs These pins...

Страница 28: ...16 2 1 Single Ended Analog Inputs The pins labeled A6 A11 are connected directly to 3 pairs of analog capable pins on the Zynq PL via an anti aliasing filter This circuit is shown in Figure 16 2 2 The...

Страница 29: ...ign via the Dynamic Reconfiguration Port DRP The DRP also provides access to voltage monitors that are present on each of the FPGA s power rails and a temperature sensor that is internal to the FPGA F...

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