2.1.3. DPS Part
2.1.4. XDFP Part
Table 2–9: New DPS Registers
Name
Sub
Dir
Sync
Reset
Range
Function
DEFL
FBOUTEN
hD3[0]
RW
VS_DEFL
0
0,1
FBOUT Enable at PWMV pin
0: PWMV to Port Mux
1: FBOUT to Port Mux
Table 2–10: Undocumented DPS Registers (already available in Dx versions)
Name
Sub
Dir
Sync
Reset
Range
Function
LLPLL
IICINCR[18:3]
h00[15:0]
RW
load_iicinc
r
32768
0..65535
HDTO Increment High
controls center frequency of LLPLL
clkhll = IICINCR* 648*10**6/1048576
beclk = clkhll / 8
16384: beclk = 1.27 MHz
174763: beclk = 13.5MHz
262144: beclk = 20.25 MHz
349525: beclk = 27MHz
524287: beclk = 40.5 MHz
IICINCR[2:0]
h01[2:0]
RW
load_iicinc
r
0
0..7
HDTO Increment Low
PPLIP[11:0]
h02[11:0]
RW
1296
0..4095
Pixel per Line Input Processing
must be equal to PPLOP !!!
ODC
PPLOP[11:0]
h17[11:0]
RW
upd_pplop
1296
0..4095
Pixel Per Line Output
must be equal to PPLIP !!!
BLE
MINRED
h3E[13]
RW
VS_DP
0
0,1
Enable Entropy Adaption
0: entropy adaption off
1: entropy adaption on
LUMAMIX
LMIXMODE
h47[14]
RW
VS_DP
1
0,1
Luminance Mixer Mode
0: static mixer
1: amplitude adaptive mixer
LMIXCOF[5:0]
h47[13:8]
RW
VS_DP
0
0..63
Luminance Mixer Coefficient
static mixer coefficient (used if LMIXMODE=0)
0: 100% peaking
...
63: 100% LTI
PIXMIX
PATTSIZE
h60[11]
RW
VS_DP
1
0,1
Test Pattern Size
0: 720 pixel/line
1: 1080 pixel/line
Table 2–11: New XDFP Registers
Name
Sub
Dir
Sync
Reset
Range
Function
Measurement
HVBLKDIS
hF2
h01C2[11]
RW
0
0,1
Horizontal & Vertical Blanking Disable
Analog RGB
NEWCALIB
hF2
h01DE[11]
RW
1
0, 1
New Calibration Method
for compatibility of different MSPH and VCTH versions
0: use old VCTH with new MSPH
1: any other combination
CIRCUIT DESCRIPTIONS