7. VCT 49xyI-C7
The VCT 49xyI-C7 is pin-compatible to VCT 49xyI-C6 and VCT 49xyI-C4.
Problem 45 has been solved. Problem 43 is partly solved: Improved internal clock suppression leads to reduced
noise floor and better video snr. Problems 53 and 54 have not been detected before D2.
VCT 49xyI-C7 includes functionality of DRX396xA-H8.
Table 7–1: Functional problems of VCT 49xyI-C7:
No.
Problem
Description
Comment
OK
18
Vertical Synchronisa-
tion
Vertical pull-in after channel
change takes too long
hardware redesign D1
workaround:
increase LPFOPOFF
D1
26
Picture Frame Blanked
Left side of picture frame is blanked
if HORPOSG<180.
hardware redesign D1
D1
34
Reset after Read
All I2C register with "reset by read"
are not functional (NMSTATUS,
LBDSTATUS, FBLACTIVE,
FBFALL, FBRISE, PFBL/G/R/B).
hardware redesign D1
D1
39
Peaking Filter
In case of PKCF=2,3, the dynamic
peaking adaption doesn’t work.
Thus the peaking signal is limited
only.
hardware redesign D1
D1
40
Bandwidth of Antialias
Filter
The bandwidth adjustment of the
antialias filter 1-6 is disturbed. This
causes wrong filter settings after
reset and/or after a modification of
TRIM_FILTER1-6
hardware redesign D1
workaround:
<0xb0 0x2f 0x00 0x01>
D1
41
SVM Overflow
The SVM output signal is not lim-
ited correctly over the full range of
SVLIM.
hardware redesign D1
workaround:
SVLIM = 31
D1
42
ADC Initialisation
Wrong initialisation of RGB ADCs
after power-on causes color mis-
match.
hardware redesign D1
workaround:
<0xb0 0x37 0x00 0xe4>
D1
43
Clock Noise
Induced harmonics of the system
clock generate visible interference
on weak IF input signals.
hardware redesign D1
46
HORPOS changes
color multiplex
When picture is shifted to the right
via HORPOS the color multiplex is
inverted.
hardware redesign D1
workaround:
HORWIDTH < 1287
D1
47
Preframe Generator
The preframe generator cannot
produce full screen background
color.
hardware redesign D1
D1
CIRCUIT DESCRIPTIONS
