www.diamondsystems.com
Zeta User Manual Rev 1.0
Page 45
Examples for 0-5V output range:
offset voltage = .003V, full-scale voltage = 5.012V, desired output voltage = 1.000V
D/A code = (1V - .003V) / (5.012V - .003V) * 65535 =
13044
offset voltage = -.003V, full-scale voltage = 4.996V, desired output voltage = 1.000V
D/A code = (1V + .003V) / (4.996V - .003V) * 65535 =
13149
Note: In this formula, the binary code scale value is 65535, not 65536. This is because the full scale voltage Vmax
was measured with the actual output code of 65535.
Note: The output values are limited to voltages between the 0 code voltage and the 65535 code voltage. If the
offset voltage is positive, you cannot output 0V.
Note: D/A codes are limited to positive values in the range 0-65535. Therefore, a positive offset voltage (output
voltage is greater than zero when D/A code = 0) cannot be corrected, since correction would require a D/A code
less than zero. This is why the formula above uses the max() function to force a minimum D/A code of zero.
14.4
Digital I/O Features
14.4.1
Overview
The 27 digital I/O lines are organized as 4 ports A, B, C, and D. Ports A, B, and C are 8 bits wide, and port D is 3 bits
wide. All ports may be configured with a jumper for either 3.3V or 5V logic levels, and all ports may also be
configured with a jumper for 10K ohm pull-up or pull-down resistors. These settings apply to all ports collectively;
it is not possible to configure some ports for 3.3V and others for 5V at the same time, or to configure some ports
for pull-up and other ports for pull-down simultaneously.
All digital I/O ports utilize logic buffers (transceivers) to provide enhanced output current capability and protect
the FPGA from faulty connections. Ports A and B utilize 8-bit transceivers, and their directions are set for all 8 bits
as a group. Ports C and D utilize 1-bit transceivers, and their directions are individually configurable for each bit.
For safety and to prevent glitches, on power up or reset, all ports reset to input mode and all port data registers
reset to all 0.
All DIO ports may operate in “normal” digital I/O mode where they are written and read
directly with their data
registers. In addition to normal mode, port B may be used for edge detection. If the input value of any bit on port
B changes, that change can drive an interrupt, which will then cause user-specified code to run. Ports C and D may
also be configured to support other features on the board, such as counter/timer I/O, PWM output, and analog
circuit triggers.
“A” Model Digital I/O
Summary
Port
Size
Direction control
Special features
A
8 bits
Bytewise
N/A
B
8 bits
Bytewise
Edge detect capability
C
8 bits
Bitwise
Counter and PWM I/O
D
3 bits
Bitwise
A/D external clock
D/A waveform external clock
14.4.2
Edge Detection Circuit
On “A” models, an edge detection circuit is available on port B. The edge detection circuit can be used to notify
the processor when a particular event occurs, such as a door opening, a switch being pressed, or a light curtain
being penetrated.
