Athena III User Manual Rev A.03
www.diamondsystems.com
Page
59
Page 1, Base + 14
Read
Calibration Status Register
Bit No.
7
6
5
4
3
2
1
0
Name
0
TDBUSY EEBUSY CALMUX
0
0
0
0
TDBUSY
TrimDAC busy indicator.
0
User may access TrimDAC
1
TrimDAC is being accessed; user must wait.
EEBUSY
EEPROM busy indicator.
0
User may access EEPROM
1
EEPROM is being accessed; user must wait.
CALMUX
Readback of calibration multiplexor enable setting:
1
Enabled.
0
Disabled.
Page 1, Base + 15
Write
EEPROM Access Key Register
The user must write the key value 0xA5 (binary 10100101) to this register each time after any change in the
states of registers bits PG1 and PG0 (base+1 bits 1-0) in order to get access to the EEPROM. This helps
prevent accidental corruption of the EEPROM contents. Once the key value is written, access to the
EEPROM remains enabled until the page bits are changed.
12.4
Page 2 Register Definitions
ADC Expanded FIFO: Base+12 (Read)
Bit:
7
6
5
4
3
2
1
0
Name:
-
-
-
-
-
-
-
ADCEXF
ADCEXF ADC expanded FIFO mode flag.
0 = Not in expanded FIFO mode.
1 = In expanded FIFO mode.
Note:
When in expanded FIFO mode, the FIFO threshold and FIFO depth bits represent the
upper eight bits of an 11-bit value.
ADC Expanded FIFO: Base+12 (Write)
Bit:
7
6
5
4
3
2
1
0
Name:
-
-
-
-
-
-
-
ADCEXF
ADCEXF ADC expanded FIFO mode flag.
0 = Not in expanded FIFO mode.
1 = In expanded FIFO mode.