Athena III User Manual Rev A.03
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42
12. DATA ACQUISITION CIRCUIT
Athena III contains a data acquisition subsystem consisting of A/D, D/A, digital I/O, and counter/timer features.
This subsystem is equivalent to a complete add-on data acquisition module.
The A/D section includes a 16-bit A/D converter, 16 input channels, and a 2048-sample FIFO. Input ranges are
programmable, and the maximum sampling rate is 200KHz. The D/A section includes four 12-bit D/A channels.
The digital I/O section includes 24 lines with programmable direction. The counter/timer section includes a 24-bit
counter/timer to control A/D sampling rates and a 16-bit counter/timer for user applications.
High-speed A/D sampling is supported with interrupts and a FIFO. The FIFO is used to store a user-selected
number of samples, and the interrupt occurs when the FIFO reaches this threshold. Once the interrupt occurs, an
interrupt routine runs and reads the data out of the FIFO. In this way the interrupt rate is reduced by a factor
equal to the size of the FIFO threshold, enabling a faster A/D sampling rate. The circuit can operate at sampling
rates of up to 200KHz, with an interrupt rate of 6.6-10KHz.
The A/D circuit uses the default (hard wired) setting of I/O base address 280h and IRQ 5. The IRQ setting can be
changed if needed. The interrupt level is changed with jumper block JP7 and also with the IRQ number in the
BIOS.
The figure on the next page shows a block diagram of the data acquisition circuit.