DG TOE10G IP, Инструкция к демонстрации

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dg_toe10gip_cpu_instruction_xilinx_en.doc
23-Aug-19 Page 41
8.5 Full duplex Test
Select ‘4’ to run full duplex test on server FPGA and client FPGA to transfer data in both
directions at the same time. User inputs test parameters through Serial console. The
sequence to run the test is shown as below.
1) On Serial console of server, input four parameters in full duplex test.
a) Input transfer size: Unit of transfer size is byte. Valid value is 0x8 - 0x7_FFFF_FFF8.
The input must be aligned to 8 and must match with transfer size in FPGA running as
client. The input is decimal unit when user inputs only digit number. Use
r can add “0x”
to be a prefix when the input is hexadecimal unit.
b) Input packet size: Unit of packet size is byte. Valid value is 8
– 8960. The input must be
aligned to 8. The input is decimal unit when user inputs only digit number. User can add
“0x” to be a prefix when the input is hexadecimal unit.
c) Input data ve
rification mode: Set ‘0’ to disable data verification or ‘1’ to enable data
verification to verify data from FPGA running as client.
It is recommended to set ‘1’ to
verify data from client.
d) Input Mode:
Mode of FPGA to transfer data. Input ‘1’ to set server mode.
2) If inputs a
re valid, “Wait open connection…” will be displayed.
3) On Serial console of client, input four test parameters in full duplex test.
a) Input transfer size: Unit of transfer size is byte. Valid value is 0x8 - 0x7_FFFF_FFF8.
The input must be aligned to 8 and must match with transfer size in FPGA running as
server (input in step 1a). The input is decimal unit when user inputs only digit number.
User can add “0x” to be a prefix when the input is hexadecimal unit.
b) Input packet size: Unit of packet size is byte. Valid value is 8
– 8960. The input must be
aligned to 8. The input is decimal unit when user inputs only digit number. User can add
“0x” to be a prefix when the input is hexadecimal unit.
c) Input data verification mode: S
et ‘0’ to disable data verification or ‘1’ to enable data
verification to verify data from FPGA running as server.
It is recommended to set ‘1’ to
verify data from server.
d) Input Mode: Mode of FPGA to transfer data.
Input ‘0’ to set client mode.
If inputs are valid, the operation will start.
4) After running client, current transfer size is displayed on both Serial consoles every
second.
5)
“Send data complete” is displayed on Serial console of client after it finishes sending data,
receiving data, and closing connection. Finally, total transfer size and performance are
displayed on both Serial consoles.
Step 4)
– 5) are repeated in forever loop until the user cancels the operation. To cancel
operation, press any keys on server Serial console and client Serial console.