DG TOE10G IP, Инструкция к демонстрации

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dg_toe10gip_cpu_instruction_xilinx_en.doc
23-Aug-19 Page 35
8.2 Reset TCPIP parameters
Select ‘1’ to reset the IP and change IP parameters.
This menu is used to change IP parameters or send reset to TOE10 IP. After user selects
this menu, the current parameters are displayed on the console. User enters
‘x’ to use same
parameters while other keys are entered to change some parameters. After the parameters
are fixed, reset signal is sent to TOE10G IP.
There are seven parameters to set in this menu. Each parameter is verified by CPU. The
parameter is updated to TOE10G IP when the input is valid. If which input is not valid, the
parameter will not change. After user inputs all parameters, IP is reset. The description of
each parameter is shown in topic 8.1(Display current parameter) and the range of each
parameter is described as follows.
Note:
1. When user needs to reset parameters on the server FPGA, the client FPGA must be also
reset. The server must be reset before the client to wait until ARP request sent by the
client.
2. Parameter of client and server must be matched, i.e.
a. Target IP of server = FPGA IP of client
b. FPGA IP of server = Target IP of client
c. Target port number of server = FPGA port number of client
d. FPGA port number of server = Target port number of client
1) Window Update Gap: Set threshold value to transmit window update packet. Valid value
is 0x00
– 0x3F (0-63). The unit size of threshold value is 1 Kbyte. Default value is 0
(disable window update feature).
2) Mode:
Input ‘0’ (client) or ‘1’ (server) to determine FPGA initialization mode. It needs to set
different mode for two FPGA boards. The 1
st
board is client (mode=
‘0’) and the 2
nd
board
is server (mode=
‘1’).
3) FPGA MAC address: Input 12 digit of h
ex value. Add “0x” as a prefix to input as hex value.
4) FPGA IP
address: A set of four decimal digits is separated by “.”. The valid range of
decimal number is 0-255.
5) FPGA port number: Valid range is 0-65535.
6) Target IP address: A set of four decimal digits like FPGA IP address.
7) Target port number: Valid range is 0-65535.
After finishing all parameter assignments, the new parameters are displayed on Serial
console. Next, reset signal is sent to the IP to initialize by using new parameters set. Finally,
“IP initialization complete” is shown after IP completes initialization process, as shown in
Figure 8-2.