26
LPC Connector
The Low Pin Count Interface was defined by Intel
®
Corporation to facilitate the industry’s tran-
sition towards legacy free systems. It allows the integration of low-bandwidth legacy I/O com-
ponents within the system, which are typically provided by a Super I/O controller. Furthermore,
it can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embed-
ded controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized
data interface, which uses a 33MHz LPC bus clock. For more information about LPC bus refer
to the Intel
®
Low Pin Count Interface Specification Revision 1.1’. The table below indicates the
pin fuctions of the LPC connector.
Pins
Pin Assignment
Pins
Pin Assignment
1
L_CLK
2
L_AD1
3
L_RST#
4
L_AD0
5
L_FRAME#
6
3V3
7
L_AD3
8
GND
9
L_AD2
10
Key
11
INT_SERIRQ
12
GND
13
5VSB
14
5V
LPC
2 1
1413
The SMBus (System Management Bus) connector is used to connect SMBus devices. It is a
multiple device bus that allows multiple chips to connect to the same bus and enable each one
to act as a master by initiating data transfer.
SMBus Connector
SMBus
1
2
5
6
SMBUS_CLK 3V3SB
SMBUS_Data
SMBUS_Alert
GND
