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Award BIOS Setup Utility
3.1.3.3 CPU & PCI Bus Control
Move the cursor to this field and press <Enter>. The following
screen will appear.
PCI Master 0 WS Write and AGP Master 0 WS Write
When enabled, writes to the PCI or AGP bus are executed with
zero wait state.
CPU-PCI Post Write and CPU-AGP Post Write
The options are Enabled and Disabled.
VLink 8x Support
Enabled
The speed of VLink which links the North Bridge
and South Bridge is 8x.
Disabled
The speed of VLink which links the North Bridge
and South Bridge is 4x.
PCI Delay Transaction
When enabled, this function frees up the PCI bus for other PCI
masters during the PCI-to-ISA transactions. This allows PCI and
ISA buses to be used more efficiently and prevents degradation
of performance on the PCI bus when ISA accesses are made.
Phoenix - AwardBIOS CMOS Setup Utility
CPU & PCI Bus Control
The settings on the screen are for reference only. Your version may not be
identical to this one.
Item Help
Menu Level
↑↓→←
Move
F6:Fail-Safe Defaults
F7:Optimized Defaults
F1:General Help
Enter:Select
F5:Previous Values
+/-/PU/PD:Value
F10:Save
ESC:Exit
PCI Master 0 WS Write
AGP Master 0 WS Write
CPU-PCI Post Write
CPU-AGP Post Write
VLink 8x Support
PCI Delay Transaction
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled