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3
Award BIOS Setup Utility
DRAM Timing
This field is used to select the timing of the DRAM.
By SPD
The EEPROM on a DIMM has SPD (Serial
Presence Detect) data structure that stores in-
formation about the module such as the
memory type, memory size, memory speed, etc.
When this option is selected, the system will
r un according to the infor mation in the
EEPROM. This option is the default setting be-
cause it provides the most stable condition for
the system. The “DRAM CAS Latency” to “Ac-
tive to CMD (Trcd)” fields will show the default
settings by SPD.
Performance
If you want the system to run at a speed faster
than the one “by SPD”, select this option.
However,
compatibility problems may occur with some
DRAMs. If you encounter any problems, please
set this field to “By SPD” or “Manual”.
3.1.3.1 DRAM Clock/Drive Control
Move the cursor to this field and press <Enter>. The following
screen will appear.
Phoenix - AwardBIOS CMOS Setup Utility
DRAM Clock/Drive Control
The settings on the screen are for reference only. Your version may not be
identical to this one.
Item Help
Menu Level
↑↓→←
Move
F6:Fail-Safe Defaults
F7:Optimized Defaults
F1:General Help
Enter:Select
F5:Previous Values
+/-/PU/PD:Value
F10:Save
ESC:Exit
DRAM Timing
DRAM CAS Latency
Bank Interleave
Precharge to Active (Trp)
Tras Non-DDR400/DDR400 (Tras)
Active to CMD (Trcd)
DRAM Burst Length
DRAM Queue Depth
DRAM Drive Strength
DRAM Drive Value
DDR DRAM Command Rate
Write Recovery Time
tWTR for DDR400 ONLY
By SPD
2.5
Disabled
5T
7T/10T
5T
4
4 level
Auto
04
2T Command
3T
3T
X
X
X
X
X
X
