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Chapter 3 Hardware Installation
28
Chapter 3
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
K
H960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
DDI
D26
DP for DP / TMDS for HDMI or DVI
DDI1_PAIR0-
D27
DP1_LANE0- for DP / TMDS1_DATA2- for HDMI or DVI
DDI
D29
DP for DP / TMDS for HDMI or DVI
DDI1_PAIR1-
D30
DP1_LANE1- for DP / TMDS1_DATA1- for HDMI or DVI
DDI
D32
DP for DP / TMDS for HDMI or DVI
DDI1_PAIR2-
D33
DP1_LANE2- for DP / TMDS1_DATA0- for HDMI or DVI
DDI
D36
DP for DP / TM
DDI1_PAIR3-
D37
DP1_LANE3- for DP / TMDS1_CLK-
DDI
C25
NC
NA
DDI1_PAIR4-
C26
NC
NA
DDI
C29
NC
NA
DDI1_PAIR5-
C30
NC
NA
DDI
C15
NC
NA
DDI1_PAIR6-
C16
NC
NA
I/O PCIE
AC coupled on Module
PD 100K to GND
(S/W IC between
Rpu/PCH)
DDI for Display Port: Differetial pairs
(DP AUX+ function if DDI1_DDC_AUX_SEL is no connect)
Half-duplex bi-directional AUX channel for services such as link
configuration or maintenance and EDID access
for DP
I/O OD CMOS
3.3V / 3.3V
PU 2.2K to 3.3V, PD 100K
to GND
(S/W IC between
Rpu/Rpd resistor)
DDI for SDVO: SDVO1_CTRLCLK (SDVO I2C clock line - to set up SDVO
peripherals.)
DDI for HDMI/DVI: HDMI1_CTRLCLK
(HDMI/DVI I2C CTRLCLK if DDI1_DDC_AUX_SEL is pulled high)
HDMI1_CTRLCLK for HDMI or DVI
I/O PCIE
AC coupled on Module
PU 100K to 3.3V
(S/W IC between
Rpu/PCH)
DDI for Display Port: DP1_AUX- Differetial pairs
(DP AUX- function if DDI1_DDC_AUX_SEL is no connect)
Half-duplex bi-directional AUX channel for services such as link
configuration or maintenance and EDID access
DP1_AUX- for DP
I/O OD CMOS
3.3V / 3.3V
PU 2.2K to 3.3V/PU 100K
to 3.3V
(S/W IC between
2.2K/100K resistor)
DDI for SDVO: SDVO1_CTRLDATA (SDVO I2C data line - to set up SDVO
peripherals.)
DDI for HDMI/DVI: HDMI1_CTRLDATA
(HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high)
HDMI1_CTRLDATA for HDMI or DVI
DDI1_HPD
C24
I CMOS
3.3V / 3.3V
PD 1M to GND
DDI for Display Port: DP1_HPD (DP Hot-Plug Detect)
DDI for HDMI/DVI: HDMI1_HPD (HDMI Hot-Plug Detect)
DP1_HPD for DP / HDMI1_HPD for HDMI or DVI
DDI1_DDC_AUX_SEL
D34
I CMOS
3.3V / 3.3V
PD 1M to GND
Selects the function of DDI1_CTRL and
DDI1_CTRLDATA_AUX-. This pin shall have a 1M pull-down to
logic ground on the Module. If this input is floating the AUX pair is
used for the DP AUX+/- signals. If pulled-high the AUX pair contains the
CRTLCLK and CTRLDATA signals.
Selects the function of DP1 AUX
±
(Low) or HDMI1 DDC
CLK/DATA(High)
The DDC_AUX_SEL pin should be routed to pin 13 of the
DisplayPort connector, to enable Dual-Mode.
When HDMI/DVI is directly done on the Carrier Board, this pin shall
be pulled to 3.3V with a 100k Ohm resistor to configure the AUX
pairs as DDC channels.
DDI
D39
DP for DP / TMDS for HDMI or DVI
DDI2_PAIR0-
D40
DP2_LANE0- for DP / TMDS2_DATA2- for HDMI or DVI
DDI
D42
DP for DP / TMDS for HDMI or DVI
DDI2_PAIR1-
D43
DP2_LANE1- for DP / TMDS2_DATA1- for HDMI or DVI
DDI
D46
DP for DP / TMDS for HDMI or DVI
DDI2_PAIR2-
D47
DP2_LANE2- for DP / TMDS2_DATA0- for HDMI or DVI
DDI
D49
DP for DP / TM
DDI2_PAIR3-
D50
DP2_LANE3- for DP / TMDS2_CLK-
I/O PCIE
AC coupled on Module
PD 100K to GND
(S/W IC between
Rpu/PCH)
DDI for Display Port: Differetial pairs
(DP AUX+ function if DDI2_DDC_AUX_SEL is no connect)
Half-duplex bi-directional AUX channel for services such as link
configuration or maintenance and EDID access
for DP
I/O OD CMOS
3.3V / 3.3V
PU 2.2K to 3.3V, PD 100K
to GND
(S/W IC between
Rpu/Rpd resistor)
DDI for HDMI/DVI: HDMI2_CTRLCLK
(HDMI/DVI I2C CTRLCLK if DDI2_DDC_AUX_SEL is pulled high)
HDMI2_CTRLCLK for HDMI or DVI
I/O PCIE
AC coupled on Module
PU 100K to 3.3V
(S/W IC between
Rpu/PCH)
DDI for Display Port: DP2_AUX- Differetial pairs
(DP AUX- function if DDI2_DDC_AUX_SEL is no connect)
Half-duplex bi-directional AUX channel for services such as link
configuration or maintenance and EDID access
DP2_AUX- for DP
I/O OD CMOS
3.3V / 3.3V
PU 2.2K to 3.3V/PU 100K
to 3.3V
(S/W IC between
2.2K/100K resistor)
DDI for HDMI/DVI: HDMI2_CTRLDATA
(HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high)
HDMI2_CTRLDATA for HDMI or DVI
DDI2_HPD
D44
I CMOS
3.3V / 3.3V
PD 1M to GND
DDI for Display Port: DP2_HPD (DP Hot-Plug Detect)
DDI for HDMI/DVI: HDMI2_HPD (HDMI Hot-Plug Detect)
DP2_HPD for DP / HDMI1_HPD for HDMI or DVI
DDI2_DDC_AUX_SEL
C34
I CMOS
3.3V / 3.3V
PD 1M to GND
Selects the function of DDI2_CTRL and
DDI2_CTRLDATA_AUX-. This pin shall have a 1M pull-down to
logic ground on the Module. If this input is floating the AUX pair is
used for the DP AUX+/- signals. If pulled-high the AUX pair contains the
CRTLCLK and CTRLDATA signals.
Selects the function of DP2 AUX
±
(Low) or HDMI2 DDC
CLK/DATA(High)
The DDC_AUX_SEL pin should be routed to pin 13 of the
DisplayPort connector, to enable Dual-Mode.
When HDMI/DVI is directly done on the Carrier Board, this pin shall
be pulled to 3.3V with a 100k Ohm resistor to configure the AUX
pairs as DDC channels.
DDI
C39
DP for DP / TMDS for HDMI or DVI
DDI3_PAIR0-
C40
DP3_LANE0- for DP / TMDS3_DATA2- for HDMI or DVI
DDI
C42
DP for DP / TMDS for HDMI or DVI
DDI3_PAIR1-
C43
DP3_LANE1- for DP / TMDS3_DATA1- for HDMI or DVI
DDI
C46
DP for DP / TMDS for HDMI or DVI
DDI3_PAIR2-
C47
DP3_LANE2- for DP / TMDS3_DATA0- for HDMI or DVI
DDI
C49
DP for DP / TM
DDI3_PAIR3-
C50
DP3_LANE3- for DP / TMDS3_CLK-
I/O PCIE
AC coupled on Module
PD 100K to GND
(S/W IC between
Rpu/PCH)
DDI for Display Port: Differetial pairs
(DP AUX+ function if DDI3_DDC_AUX_SEL is no connect)
Half-duplex bi-directional AUX channel for services such as link
configuration or maintenance and EDID access
for DP
I/O OD CMOS
3.3V / 3.3V
PU 2.2K to 3.3V, PD 100K
to GND
(S/W IC between
Rpu/Rpd resistor)
DDI for HDMI/DVI: HDMI3_CTRLCLK
(HDMI/DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high)
HDMI3_CTRLCLK for HDMI or DVI
I/O PCIE
AC coupled on Module
PU 100K to 3.3V
(S/W IC between
Rpu/PCH)
DDI for Display Port: DP3_AUX- Differetial pairs
(DP AUX- function if DDI3_DDC_AUX_SEL is no connect)
DP3_AUX- for DP
I/O OD CMOS
3.3V / 3.3V
PU 2.2K to 3.3V/PU 100K
to 3.3V
(S/W IC between
2.2K/100K resistor)
DDI for HDMI/DVI: HDMI3_CTRLDATA
(HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high)
HDMI3_CTRLDATA for HDMI or DVI
DDI3_HPD
C44
I CMOS
3.3V / 3.3V
PD 1M
Ω
to GND
DDI for Display Port: DP3_HPD (DP Hot-Plug Detect)
DDI for HDMI/DVI: HDMI3_HPD (HDMI Hot-Plug Detect)
DP3_HPD for DP / HDMI1_HPD for HDMI or DVI
DDI3_DDC_AUX_SEL
C38
I CMOS
3.3V / 3.3V
PD 1M
Ω
to GND
Selects the function of DDI3_CTRL and
DDI3_CTRLDATA_AUX-. This pin shall have a 1M pull-down to
logic ground on the Module. If this input is floating the AUX pair is
used for the DP AUX+/- signals. If pulled-high the AUX pair contains the
CRTLCLK and CTRLDATA signals.
Selects the function of DP3 AUX
±
(Low) or HDMI3 DDC
CLK/DATA(High)
The DDC_AUX_SEL pin should be routed to pin 13 of the
DisplayPort connector, to enable Dual-Mode.
When HDMI/DVI is directly done on the Carrier Board, this pin shall
be pulled to 3.3V with a 100k Ohm resistor to configure the AUX
pairs as DDC channels.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
K
H960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
SER0_TX
A98
O CMOS
5V/12V
General purpose serial port 0 transmitter
Transmit Line for Serial Port 0 ; PD 4.7K
Ω
SER0_RX
A99
I CMOS
5V/12V
PU 10K
Ω
to 3.3V
General purpose serial port 0 receiver
Receive Line for Serial Port 0
SER1_TX
A101
O CMOS
5V/12V
General purpose serial port 1 transmitter
Transmit Line for Serial Port 1 ; PD 4.7KΩ
SER1_RX
A102
I CMOS
5V/12V
PU 10K
Ω
to 3.3V
General purpose serial port 1 receiver
Receive Line for Serial Port 1
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
K
H960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
I2C_CK
B33
I/O OD CMOS
3.3V Suspend/3.3V
PU 2.2K to 3.3V Suspend General purpose I2C port clock output
General Purpose I2C Clock output
I2C_DAT
B34
I/O OD CMOS
3.3V Suspend/3.3V
PU 2.2K to 3.3V Suspend General purpose I2C port data I/O line
General Purpose I2C data I/O line.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
K
H960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
SPKR
B32
O CMOS
3.3V / 3.3V
Output for audio enunciator - the "speaker" in PC-AT systems.
This port provides the PC beep signal and is mostly intended for
debugging purposes.
Output used to control an external FET or a logic gate to drive an
external PC speaker.
WDT
B27
O CMOS
3.3V / 3.3V
Output indicating that a watchdog time-out event has occurred.
Output indicating that a watchdog time-out event has occurred.
FAN_PW
M
OUT
B101
O CMOS
3.3V / 12V
RSV PD 100K
Ω
to GND
Fan speed control. Uses the Pulse Width Modulation (PWM) technique to
control the fan's RPM.
Fan speed control. Uses the Pulse Width Modulation (PWM)
technique to control the fan’s RPM.
FAN_TACHIN
B102
I OD CMOS
3.3V / 12V
PU 47K
Ω
to 3.3V
Fan tachometer input for a fan with a two pulse output.
Fan tachometer input for a fan with a two pulse output.
TPM_PP
A96
I CMOS
3.3V / 3.3V
PD 100K
Ω
to GND.
Trusted Platform Module (TPM) Physical Presence pin. Active high.
TPM chip has an internal pull down. This signal is used to indicate Physical
Presence to the TPM.
Trusted Platform Module (TPM) Physical Presence pin. Active high.
TPM chip has an internal pull down. Thissignal is used to indicate
Physical Presence to the TPM.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
K
H960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
PWRBTN#
B12
I CMOS
3.3V Suspend/3.3V
PU 10K
Ω
to 3.3V Suspend
A falling edge creates a power button event. Power button events can
be used to bring a system out of S5 soft off and other suspend states,
as well as powering the system down.
Power button low active signal used to wake up the system from S5
state (soft off). This signal is triggered on the falling edge.
SYS_RESET#
B49
I CMOS
3.3V Suspend/3.3V
PU 10K
Ω
to 3.3V Suspend
Reset button input. Active low request for Module to reset and reboot.
May be falling edge sensitive. For situations when SYS_RESET# is
not able to reestablish control of the system, PWR_OK or a power
cycle may be used.
Reset button input. Active low request for Module to reset and
reboot. May be falling edge sensitive. For situations when
SYS_RESET# is not able to reestablish control of the system,
PWR_OK or a power cycle may be used.
CB_RESET#
B50
O CMOS
3.3V Suspend/3.3V
PD 100K
Ω
to GND
Reset output from Module to Carrier Board. Active low. Issued by
Module chipset and may result from a low SYS_RESET# input, a low
PWR_OK input, a VCC_12V power input that falls below the minimum
specification, a watchdog timeout, or may be initiated by the Module
software.
Reset output signal from Module to Carrier Board. This signal may be
driven low by the Module to reset external components located on
the Carrier Board.
PWR_OK
B24
I CMOS
3.3V / 3.3V
PU 10K
Ω
to 3.3V
Power OK from main power supply. A high value indicates that the
power is good. This signal can be used to hold off Module startup to
allow Carrier based FPGAs or other configurable devices time to be
programmed.
Power OK status signal generated by the ATX power supply to notify
the Module that the DC operating voltages are within the ranges
required for proper operation.
SUS_STAT#
B18
O CMOS
3.3V Suspend/3.3V
Indicates imminent suspend operation; used to notify LPC devices.
Suspend status signal to indicate that the system will be entering a
low power state soon. It can be used by other peripherals on the
Carrier Board as an indication that they should go into power-down
mode.
SUS_S3#
A15
O CMOS
3.3V Suspend/3.3V
PD 100KΩ to GND
Indicates system is in Suspend to RAM state. Active low output. An
inverted copy of SUS_S3# on the Carrier Board may be used to enable
the non-standby power on a typical ATX supply.
S3 Sleep control signal indicating that the system resides in S3 state
(Suspend to RAM).
SUS_S4#
A18
O CMOS
3.3V Suspend/3.3V
PD 100KΩ to GND
Indicates system is in Suspend to Disk state. Active low output.
S4 Sleep control signal indicating that the system resides in S4 state
(Suspend to Disk).
SUS_S5#
A24
O CMOS
3.3V Suspend/3.3V
PD 100KΩ to GND
Indicates system is in Soft Off state.
S5 Sleep Control signal indicating that the system resides in S5 State
(Soft Off).
WAKE0#
B66
I CMOS
3.3V Suspend/3.3V
PU 10K
Ω
to 3.3V Suspend PCI Express wake up signal.
PCI Express wake-up event signal.
WAKE1#
B67
I CMOS
3.3V Suspend/3.3V
Integrate PU @PCH
General purpose wake up signal. May be used to implement wake-up
on PS2 keyboard or mouse activity.
General purpose wake-up signal.
BATLOW#
A27
I CMOS
3.3V Suspend/ 3.3V
PU 10KΩ to 3.3V Suspend
Indicates that external battery is low.
This port provides a battery-low signal to the Module for orderly
transitioning to power saving or power cut-off ACPI modes.
Battery low input. This signal may be driven low by external circuitry
to signal that the system battery is low. It also can be used to signal
some other external power management event.
LID#
A103
I OD CMOS
3.3V Suspend/12V
PU 47K
Ω
to 3.3V Suspend
LID switch. Low active signal used by the ACPI operating system for a LID
switch.
LID switch.
Low active signal used by the ACPI operating system for a LID
switch.
SLEEP#
B103
I OD CMOS
3.3V Suspend/12V
PU 47K
Ω
to 3.3V Suspend
Sleep button. Low active signal used by the ACPI operating system to
bring the
system to sleep state or to wake it up again.
Sleep button.
Low active signal used by the ACPI operating system to bring the
system to sleep state or to wake it up again.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
K
H960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
THRM#
B35
I CMOS
3.3V / 3.3V
PU 10K
Ω
to 3.3V
Input from off-Module temp sensor indicating an over-temp situation.
Thermal Alarm active low signal generated by the external hardware
to indicate an over temperature situation. This signal can be used to
initiate thermal throttling.
THRMTRIP#
A35
O CMOS
3.3V / 3.3V
PU 10K
Ω
to 3.3V
Active low output indicating that the CPU has entered thermal shutdown.
Thermal Trip indicates an overheating condition of the processor. If
'THRMTRIP#' goes active the system immediately transitions to the
S5 State (Soft Off).
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
K
H960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
SMB_CK
B13
I/O OD CMOS
3.3V Suspend/3.3V
PU 2.2K
Ω
to 3.3V
Suspend
System Management Bus bidirectional clock line.
System Management Bus bidirectional clock line
SMB_DAT
B14
I/O OD CMOS
3.3V Suspend/3.3V
PU 2.2K
Ω
to 3.3V
Suspend
System Management Bus bidirectional data line.
System Management bidirectional data line.
SMB_ALERT#
B15
I CMOS
3.3V Suspend/3.3V
PU 2.2K
Ω
to 3.3V
Suspend
System Management Bus Alert – active low input can be used to generate
an SMI# (System Management Interrupt) or to wake the system.
System Management Bus Alert
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
K
H960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
GPO0
A93
GPO1
B54
GPO2
B57
GPO3
B63
GPI0
A54
PU 47K
Ω
to 3.3V
GPI1
A63
PU 47K
Ω
to 3.3V
GPI2
A67
PU 47K
Ω
to 3.3V
GPI3
A85
PU 47K
Ω
to 3.3V
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
K
H960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
VCC_12V
A104~A109
B104~B109
C104~C109
D104~D109
Power
Primary power input: +12V nominal. All available VCC_12V pins on the
connector(s) shall be used.
VCC_5V_SBY
B84~B87
Power
Standby power input: +5.0V nominal. If VCC5_SBY is used, all
available VCC_5V_SBY pins on the connector(s) shall be used. Only
used for standby and suspend functions. May be left unconnected if
these functions are not used in the system design.
VCC_RTC
A47
Power
Real-time clock circuit-power input. Nom3.0V.
GND
A1, A11, A21, A31,
A41, A51, A57,
A60, A66, A70,
A80, A90, A100,
A110, B1, B11, B21
,B31, B41, B51,
B60, B70, B80,
B90, B100, B110,
C1, C2, C5, C8,
C11, C14, C21,
C31, C41, C51,
C60, C70, C73,
C76, C80, C84,
C87, C90, C93,
C96, C100, C103,
C110, D1, D2, D5,
D8, D11, D14,
D21, D31,
D41,D51, D60,
D67, D70, D73,
D76, D80, D84,
D87, D90, D93,
D96, D100, D103,
D110
Power
Ground - DC power and signal and AC signal return path.
All available GND connector pins shall be used and tied to Carrier Board
GND plane.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
K
H960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
TYPE0#
C54
PDS
N.C.
TYPE1#
C57
PDS
N.C.
TYPE2#
D57
PDS
PD 0
Ω
to GND
TYPE10#
A97
PDS
N.C.
Dual use pin. Indicates to the Carrier Board that a Type 10 Module is
installed. Indicates to the Carrier that a Rev 1.0/2.0 Module is installed
TYPE10#
NC Pin-out R2.0
PD Pin-out Type 10 pull down to ground with 47K resistor
12V Pin-out R1.0
This pin is reclaimed from the VCC_12V pool. In R1.0 Modules this pin will
connect to other VCC_12V pins. In R2.0 this pin is defined as a no connect
for types 1-6. A Carrier can detect a R1.0 Module by the presence of 12V
on this pin. R2.0 Module types 1-6 will no connect this pin. Type 10
Modules shall pull this pin to ground through a 47K resistor.
Indicates to the Carrier Board that a Type 10 Module is installed.
Indicates to the Carrier Board, that a Rev 1.0/2.0 Module is installed.
TYPE10#
NC Pin-out R2.0
PD Pin-out Type 10 pull down to ground with 47k
12V Pin-out R1.0
Power and GND Signal
s and
Descriptions
Module type Signal
s and
Descriptions
TYPE2# TYPE1# TYPE0#
X X X pin out Type 1
NC NC NC pin out Type 2
NC NC GND pin out Type 3 (no IDE)
NC GND NC pin out Type 4 (no PCI)
NC GND GND pin out Type 5 (no IDE, no PCI)
GND NC NC pin out Type 6 (no IDE, no PCI)
The Type pins indicate the COM Express pin-out type of the
Module. To indicate the Module's pin-out type, the pins are
either not connected or strapped to ground on the Module.
The Carrier Board has to implement additional logic, which
prevents the system to switch power on, if a Module with an
incompatible pin-out type is detected.
GPIO Signals
and
Descriptions
O CMOS
3.3V / 3.3V
General purpose output pins. Upon a hardware reset, these outputs should
be low.
General Purpose Outputs for system specific usage.
I CMOS
3.3V / 3.3V
General purpose input pins. Pulled high internally on the Module.
General Purpose Input for system specific usage. The signals are
pulled up by the Module.
Serial Interface Signals
and
Descriptions
I2C Signal
s and
Descriptions
Miscellaneous Signal
s and
Descriptions
Power and System Management Signals
and
Descriptions
Thermal Protection Signals
and
Descriptions
SMBUS Signals
and
Descriptions
O PCIE
AC coupled off Module
DDI for Display Port: DP3_LANE 3 differential pairs
DDI for HDMI/DVI: TMDS3_CLK differential pairs
DDI3_CTRL
C36
DDI3_CTRLCLK_AUX-
C37
DDI for Display Port: DP3_LANE 0 differential pairs
DDI for HDMI/DVI: TMDS3_DATA lanes 2 differential pairs
O PCIE
AC coupled off Module
DDI for Display Port: DP3_LANE 1 differential pairs
DDI for HDMI/DVI: TMDS3_DATA lanes 1 differential pairs
O PCIE
AC coupled off Module
DDI for Display Port: DP3_LANE 2 differential pairs
DDI for HDMI/DVI: TMDS3_DATA lanes 0 differential pairs
DDI2_CTRL
C32
DDI2_CTRLCLK_AUX-
C33
O PCIE
AC coupled off Module
O PCIE
AC coupled off Module
DDI for Display Port: DP2_LANE 2 differential pairs
DDI for HDMI/DVI: TMDS2_DATA lanes 0 differential pairs
O PCIE
AC coupled off Module
DDI for Display Port: DP2_LANE 3 differential pairs
DDI for HDMI/DVI: TMDS2_CLK differential pairs
O PCIE
AC coupled off Module
DDI for Display Port: DP2_LANE 0 differential pairs
DDI for HDMI/DVI: TMDS2_DATA lanes 2 differential pairs
O PCIE
AC coupled off Module
DDI for Display Port: DP2_LANE 1 differential pairs
DDI for HDMI/DVI: TMDS2_DATA lanes 1 differential pairs
I PCIE
AC coupled off Module
DDI for SDVO: SDVO1_FLDSTALL± differential pair
(Serial Digital Video Field Stall input differential pair.)
DDI1_CTRL
D15
DDI1_CTRLCLK_AUX-
D16
I PCIE
AC coupled off Module
DDI for SDVO: SDVO1_INT± differential pair
(Serial Digital Video B interrupt input differential pair)
I PCIE
AC coupled off Module
DDI for SDVO: SDVO1_TVCLKIN± differential pair
(Serial Digital Video TVOUT synchronization clock input differential pair.)
O PCIE
AC coupled off Module
DDI for Display Port: DP1_LANE 2 differential pairs
DDI for SDVO: SDVO1_BLU± differential pair (Serial Digital Video blue
output)
DDI for HDMI/DVI: TMDS1_DATA lanes 0 differential pairs
O PCIE
AC coupled off Module
DDI for Display Port: DP1_LANE 3 differential pairs
DDI for SDVO: SDVO1_CK± differential pair (Serial Digital Video clock
output)
DDI for HDMI/DVI: TMDS1_CLK differential pairs
O PCIE
AC coupled off Module
DDI for Display Port: DP1_LANE 0 differential pairs
DDI for SDVO: SDVO1_RED± differential pair (Serial Digital Video red
output)
DDI for HDMI/DVI: TMDS1_DATA lanes 2 differential pairs
O PCIE
AC coupled off Module
DDI for Display Port: DP1_LANE 1 differential pairs
DDI for SDVO: SDVO1_GRN± differential pair (Serial Digital Video green
output)
DDI for HDMI/DVI: TMDS1_DATA lanes 1 differential pairs
DDI Signals
and
Descriptions
Pin Types
I Input to the Module
O Output from the Module
I/O Bi-directional input / output signal
OD Open drain output
RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.
