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Chapter 3 Hardware Installation
19
Chapter 3
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
AC/HDA_RST#
A30
O CMOS
3.3V Suspend/3.3V
series 33
Ω
resistor
Reset output to CODEC, active low.
CODEC Reset.
AC/HDA_SYNC
A29
O CMOS
3.3V/3.3V
series 33
Ω
resistor
Sample-synchronization signal to the CODEC(s).
Serial Sample Rate Synchronization.
AC/HDA_BITCLK
A32
I/O CMOS
3.3V/3.3V
series 33
Ω
resistor
Serial data clock generated by the external CODEC(s).
24 MHz Serial Bit Clock for HDA CODEC.
AC/HDA_SDOUT
A33
O CMOS
3.3V/3.3V
series 33
Ω
resistor
Serial TDM data output to the CODEC.
Audio Serial Data Output Stream.
AC/HDA_SDIN0
B30
I/O CMOS
3.3V Suspend/3.3V
AC/HDA_SDIN1
B29
I/O CMOS
3.3V Suspend/3.3V
AC/HDA_SDIN2
B28
I/O CMOS
3.3V Suspend/3.3V
NC
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
GB
A13
I/O Analog
3.3V max Suspend
GBE0_MDI0-
A12
I/O Analog
3.3V max Suspend
GB
A10
I/O Analog
3.3V max Suspend
GBE0_MDI1-
A9
I/O Analog
3.3V max Suspend
GB
A7
I/O Analog
3.3V max Suspend
GBE0_MDI2-
A6
I/O Analog
3.3V max Suspend
GB
A3
I/O Analog
3.3V max Suspend
GBE0_MDI3-
A2
I/O Analog
3.3V max Suspend
GBE0_ACT#
B2
OD CMOS
3.3V Suspend/3.3V
Gigabit Ethernet Controller 0 activity indicator, active low.
Ethernet controller 0 activity indicator, active low.
GBE0_LINK#
A8
OD CMOS
3.3V Suspend/3.3V
Gigabit Ethernet Controller 0 link indicator, active low.
Ethernet controller 0 link indicator, active low.
GBE0_LINK100#
A4
OD CMOS
3.3V Suspend/3.3V
Gigabit Ethernet Controller 0 100 Mbit / sec link indicator, active low.
Ethernet controller 0 100Mbit/sec link indicator, active low.
GBE0_LINK1000#
A5
OD CMOS
3.3V Suspend/3.3V
Gigabit Ethernet Controller 0 1000 Mbit / sec link indicator, active low. Ethernet controller 0 1000Mbit/sec link indicator, active low.
GBE0_CTREF
A14
REF
GND min 3.3V max
NC
Reference voltage for Carrier Board Ethernet channel 0 magnetics
center
tap. The reference voltage is determined by the requirements of the
Module PHY and may be as low as 0V and as high as 3.3V.
The reference voltage output shall be current limited on the Module.
In
Reference voltage for Carrier Board Ethernet channel 0
magnetics center tap.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
S
A16
O SATA
AC coupled on Module
AC Coupling capacitor
SATA0_TX-
A17
O SATA
AC coupled on Module
AC Coupling capacitor
S
A19
I SATA
AC coupled on Module
AC Coupling capacitor
SATA0_RX-
A20
I SATA
AC coupled on Module
AC Coupling capacitor
S
B16
O SATA
AC coupled on Module
AC Coupling capacitor
SATA1_TX-
B17
O SATA
AC coupled on Module
AC Coupling capacitor
S
B19
I SATA
AC coupled on Module
AC Coupling capacitor
SATA1_RX-
B20
I SATA
AC coupled on Module
AC Coupling capacitor
S
A22
O SATA
AC coupled on Module
AC Coupling capacitor
SATA2_TX-
A23
O SATA
AC coupled on Module
AC Coupling capacitor
S
A25
I SATA
AC coupled on Module
AC Coupling capacitor
SATA2_RX-
A26
I SATA
AC coupled on Module
AC Coupling capacitor
S
B22
O SATA
AC coupled on Module
AC Coupling capacitor
SATA3_TX-
B23
O SATA
AC coupled on Module
AC Coupling capacitor
S
B25
I SATA
AC coupled on Module
AC Coupling capacitor
SATA3_RX-
B26
I SATA
AC coupled on Module
AC Coupling capacitor
(S)ATA_ACT#
A28
I/O CMOS
3.3V / 3.3V
PU 10K
to 3.3V
ATA (parallel and serial) or SAS activity indicator, active low.
Serial ATA activity LED. Open collector output pin driven during
SATA command activity.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
P
A68
AC Coupling capacitor
PCIE_TX0-
A69
AC Coupling capacitor
P
B68
PCIE_RX0-
B69
P
A64
AC Coupling capacitor
PCIE_TX1-
A65
AC Coupling capacitor
P
B64
PCIE_RX1-
B65
P
A61
AC Coupling capacitor
PCIE_TX2-
A62
AC Coupling capacitor
P
B61
PCIE_RX2-
B62
P
A58
AC Coupling capacitor
PCIE_TX3-
A59
AC Coupling capacitor
P
B58
PCIE_RX3-
B59
P
A55
AC Coupling capacitor
PCIE_TX4-
A56
AC Coupling capacitor
P
B55
PCIE_RX4-
B56
P
A52
AC Coupling capacitor
PCIE_TX5-
A53
AC Coupling capacitor
P
B52
PCIE_RX5-
B53
P
D19
AC Coupling capacitor
PCIE_TX6-
D20
AC Coupling capacitor
P
C19
PCIE_RX6-
C20
P
D22
AC Coupling capacitor
PCIE_TX7-
D23
AC Coupling capacitor
P
C22
PCIE_RX7-
C23
PCIE_
A88
PCIE_CLK_REF-
A89
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
D52
AC Coupling capacitor
PEG_TX0-
D53
AC Coupling capacitor
C52
PEG_RX0-
C53
D55
AC Coupling capacitor
PEG_TX1-
D56
AC Coupling capacitor
C55
PEG_RX1-
C56
D58
AC Coupling capacitor
PEG_TX2-
D59
AC Coupling capacitor
C58
PEG_RX2-
C59
D61
AC Coupling capacitor
PEG_TX3-
D62
AC Coupling capacitor
C61
PEG_RX3-
C62
D65
AC Coupling capacitor
PEG_TX4-
D66
AC Coupling capacitor
C65
PEG_RX4-
C66
D68
AC Coupling capacitor
PEG_TX5-
D69
AC Coupling capacitor
C68
PEG_RX5-
C69
D71
AC Coupling capacitor
PEG_TX6-
D72
AC Coupling capacitor
C71
PEG_RX6-
C72
D74
AC Coupling capacitor
PEG_TX7-
D75
AC Coupling capacitor
C74
PEG_RX7-
C75
D78
AC Coupling capacitor
PEG_TX8-
D79
AC Coupling capacitor
C78
PEG_RX8-
C79
D81
AC Coupling capacitor
PEG_TX9-
D82
AC Coupling capacitor
C81
PEG_RX9-
C82
P
D85
AC Coupling capacitor
PEG_TX10-
D86
AC Coupling capacitor
P
C85
PEG_RX10-
C86
P
D88
AC Coupling capacitor
PEG_TX11-
D89
AC Coupling capacitor
P
C88
PEG_RX11-
C89
P
D91
AC Coupling capacitor
PEG_TX12-
D92
AC Coupling capacitor
P
C91
PEG_RX12-
C92
P
D94
AC Coupling capacitor
PEG_TX13-
D95
AC Coupling capacitor
P
C94
PEG_RX13-
C95
P
D98
AC Coupling capacitor
PEG_TX14-
D99
AC Coupling capacitor
P
C98
PEG_RX14-
C99
P
D101
AC Coupling capacitor
PEG_TX15-
D102
AC Coupling capacitor
P
C101
PEG_RX15-
C102
PEG_LANE_RV#
D54
I CMOS
3.3V / 3.3V
PU 10K
Ω
to 3V3
PCI Express Graphics lane reversal input strap.
Pull low on the Carrier board to reverse lane order.
PCI Express Graphics lane reversal input strap.
Pull low on the carrier board to reverse lane order.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
EXCD0_CPPE#
A49
I CMOS
3.3V /3.3V
PU 10k to 3.3V
PCI ExpressCard: PCI Express capable card request, active low, one
per card
PCI ExpressCard0: PCI Express capable card request, active low,
one per card
EXCD0_PERST#
A48
O CMOS
3.3V /3.3V
PCI ExpressCard: reset, active low, one per card
PCI ExpressCard0: reset, active low, one per card
EXCD1_CPPE#
B48
I CMOS
3.3V /3.3V
PU 10k to 3.3V
PCI ExpressCard: PCI Express capable card request, active low, one
percard
PCI ExpressCard1: PCI Express capable card request, active low,
one per card
EXCD1_PERST#
B47
O CMOS
3.3V /3.3V
PCI ExpressCard: reset, active low, one per card
PCI ExpressCard1: reset, active low, one per card
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
USB0+
A46
USB Port 0, data + or D+
USB0-
A45
USB Port 0, data - or D-
USB1+
B46
USB Port 1, data + or D+
USB1-
B45
USB Port 1, data - or D-
USB2+
A43
USB Port 2, data + or D+
USB2-
A42
USB Port 2, data - or D-
USB3+
B43
USB Port 3, data + or D+
USB3-
B42
USB Port 3, data - or D-
USB4+
A40
USB Port 4, data + or D+
USB4-
A39
USB Port 4, data - or D-
USB5+
B40
USB Port 5, data + or D+
USB5-
B39
USB Port 5, data - or D-
USB6+
A37
USB Port 6, data + or D+
USB6-
A36
USB Port 6, data - or D-
USB7+
B37
USB Port 7, data + or D+
USB7-
B36
USB Port 7, data - or D-
USB_0_1_OC#
B44
I CMOS
3.3V Suspend/3.3V
PU 10K
to 3.3V
Suspend
USB over-current sense, USB channels 0 and 1. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
USB over-current sense, USB ports 0 and 1.
USB_2_3_OC#
A44
I CMOS
3.3V Suspend/3.3V
PU 10K
to 3.3V
Suspend
USB over-current sense, USB channels 2 and 3. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
USB over-current sense, USB ports 2 and 3.
USB_4_5_OC#
B38
I CMOS
3.3V Suspend/3.3V
PU 10K
to 3.3V
Suspend
USB over-current sense, USB channels 4 and 5. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
USB over-current sense, USB ports 4 and 5.
USB_6_7_OC#
A38
I CMOS
3.3V Suspend/3.3V
PU 10K
to 3.3V
Suspend
USB over-current sense, USB channels 6 and 7. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
USB over-current sense, USB ports 6 and 7.
US
D4
AC Coupling capacitor
USB Port 0, SuperSpeed TX +
USB_SSTX0-
D3
AC Coupling capacitor
USB Port 0, SuperSpeed TX -
US
C4
USB Port 0, SuperSpeed RX +
USB_SSRX0-
C3
USB Port 0, SuperSpeed RX -
US
D7
AC Coupling capacitor
USB Port 1, SuperSpeed TX +
USB_SSTX1-
D6
AC Coupling capacitor
USB Port 1, SuperSpeed TX -
US
C7
USB Port 1, SuperSpeed RX +
USB_SSRX1-
C6
USB Port 1, SuperSpeed RX -
US
D10
AC Coupling capacitor
USB Port 2, SuperSpeed TX +
USB_SSTX2-
D9
AC Coupling capacitor
USB Port 2, SuperSpeed TX -
US
C10
USB Port 2, SuperSpeed RX +
USB_SSRX2-
C9
USB Port 2, SuperSpeed RX -
US
D13
AC Coupling capacitor
USB Port 3, SuperSpeed TX +
USB_SSTX3-
D12
AC Coupling capacitor
USB Port 3, SuperSpeed TX -
US
C13
USB Port 3, SuperSpeed RX +
USB_SSRX3-
C12
USB Port 3, SuperSpeed RX -
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
/
A71
LVDS_A0-/eDP_TX2-
A72
/
A73
LVDS_A1-/eDP_TX1-
A74
/
A75
LVDS_A2-/eDP_TX0-
A76
A78
LVDS_A3-
A79
LV/
A81
LVDS_A_CK-/eDP_TX3-
A82
B71
LVDS_B0-
B72
B73
LVDS_B1-
B74
B75
LVDS_B2-
B76
B77
LVDS_B3-
B78
LV
B81
LVDS_B_CK-
B82
LVDS_VDD_EN/eDP_VDD_EN
A77
O CMOS
3.3V / 3.3V
LVDS panel / eDP power enable
LVDS flat panel power enable.
eDP power enable
LVDS_BKLT_EN/eDP_BKLT_EN
B79
O CMOS
3.3V / 3.3V
LVDS panel / eDP backlight enable
LVDS flat panel backlight enable high active signal
eDP backlight enable
LVDS_BKLT_CTRL/eDP_BKLT_CTRL
B83
O CMOS
3.3V / 3.3V
PD 100K
to GND
LVDS panel / eDP backlight brightness control
LVDS flat panel backlight brightness control
EDP backlight brightness control
LVDS_I2C_CK/
A83
I/O OD CMOS
3.3V / 3.3V
PU 2.2K
to 3.3V
I2C clock output for LVDS display use / eDP AUX+
DDC I2C clock signal used for flat panel detection and control.
eDP auxiliary lane +
LVDS_I2C_DAT/eDP_AUX-
A84
I/O OD CMOS
3.3V / 3.3V
PU 2.2K
to 3.3V
I2C data line for LVDS display use / eDP AUX-
DDC I2C data signal used for flat panel detection and control.
eDP auxiliary lane -
RSVD/eDP_HPD
A87
I CMOS
3.3V / 3.3V
RSV PD 100K
Ω
to GND
eDP_HPD:Detection of Hot Plug / Unplug and notification of the link
layer
eDP_HPD: Detection of Hot Plug / Unplug and notification of the
link layer
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
LPC_AD0
B4
LPC_AD1
B5
LPC_AD2
B6
LPC_AD3
B7
LPC_FRAME#
B3
O CMOS
3.3V / 3.3V
LPC frame indicates the start of an LPC cycle
LPC frame indicates start of a new cycle or termination of a
broken cycle.
LPC_DRQ0#
B8
PU 10K to 3.3V, not
support.
LPC_DRQ1#
B9
PU 10K to 3.3V, not
support.
LPC_SERIRQ
A50
I/O CMOS
3.3V / 3.3V
PU 10K to 3.3V
LPC serial interrupt
LPC serialized IRQ.
LPC_CLK
B10
O CMOS
3.3V / 3.3V
series 22
Ω
resistor
LPC clock output - 33MHz nominal
LPC clock output 33MHz.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
SPI_CS#
B97
O CMOS
3.3V Suspend/3.3V
Chip select for Carrier Board SPI - may be sourced from chipset SPI0 or
SPI1
Chip select for Carrier Board SPI – may be sourced from chipset
SPI0 or SPI1
SPI_MISO
A92
I CMOS
3.3V Suspend/3.3V
Data in to Module from Carrier SPI
Data in to Module from Carrier SPI
SPI_MOSI
A95
O CMOS
3.3V Suspend/3.3V
Data out from Module to Carrier SPI
Data out from Module to Carrier SPI
SPI_CLK
A94
O CMOS
3.3V Suspend/3.3V
Clock from Module to Carrier SPI
Clock from Module to Carrier SPI
SPI_POWER
A91
O
3.3V Suspend/3.3V
Power supply for Carrier Board SPI – sourced from Module – nominally
3.3V. The Module shall provide a minimum of 100mA on SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER. SPI_POWER
shall only be used to power SPI devices on the Carrier Board.
Power supply for Carrier Board SPI – sourced from Module –
nominally 3.3V. The Module shall provide a minimum of 100mA
on SPI_POWER. Carriers shall use less than 100mA of
SPI_POWER. SPI_POWER shall only be used to power SPI
devices on the Carrier.
BIOS_DIS0#
A34
PU 10K
Ω
to 3V3 Suspend.
Selection strap to determine the BIOS boot device.
The Carrier should only float these or pull them low, please refer
to for strapping options of BIOS disable signals.
BIOS_DIS1#
B88
PU 10K
Ω
to 3V3 Suspend.
Selection strap to determine the BIOS boot device.
The Carrier should only float these or pull them low.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
VGA_RED
B89
O Analog
Analog
PD 150
to GND
Red for monitor. Analog DAC output, designed to drive a 37.5
Ω
equivalent load.
Red component of analog DAC monitor output, designed to drive
a 37.5
Ω
equivalent load.
VGA_GRN
B91
O Analog
Analog
PD 150
to GND
Green for monitor. Analog DAC output, designed to drive a 37.5
Ω
equivalent load.
Green component of analog DAC monitor output, designed to
drive a 37.5
Ω
equivalent load.
VGA_BLU
B92
O Analog
Analog
PD 150
to GND
Blue for monitor. Analog DAC output, designed to drive a 37.5
Ω
equivalent load.
Blue component of analog DAC monitor output, designed to
drive a 37.5
Ω
equivalent load.
VGA_HSYNC
B93
O CMOS
3.3V / 3.3V
Horizontal sync output to VGA monitor
Horizontal sync output to VGA monitor.
VGA_VSYNC
B94
O CMOS
3.3V / 3.3V
Vertical sync output to VGA monitor
Vertical sync output to VGA monitor.
VGA_I2C_CK
B95
I/O OD CMOS
3.3V / 3.3V
PU 2.2K
to 3.3V
DDC clock line (I2C port dedicated to identify VGA monitor
capabilities)
DDC clock line (I2C port dedicated to identify VGA monitor
capabilities).
VGA_I2C_DAT
B96
I/O OD CMOS
3.3V / 3.3V
PU 2.2K
to 3.3V
DDC data line.
DDC data line.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
DDI
D26
DP for DP / TMDS for HDMI or DVI
DDI1_PAIR0-
D27
DP1_LANE0- for DP / TMDS1_DATA2- for HDMI or DVI
DDI
D29
DP for DP / TMDS for HDMI or DVI
DDI1_PAIR1-
D30
DP1_LANE1- for DP / TMDS1_DATA1- for HDMI or DVI
DDI
D32
DP for DP / TMDS for HDMI or DVI
DDI1_PAIR2-
D33
DP1_LANE2- for DP / TMDS1_DATA0- for HDMI or DVI
DDI
D36
DP for DP / TM
DDI1_PAIR3-
D37
DP1_LANE3- for DP / TMDS1_CLK-
DDI
C25
NC
NA
DDI1_PAIR4-
C26
NC
NA
DDI
C29
NC
NA
DDI1_PAIR5-
C30
NC
NA
DDI
C15
NC
NA
DDI1_PAIR6-
C16
NC
NA
I PCIE
DDI for Display Port: DP1_LANE 0 differential pairs
DDI for SDVO: SDVO1_RED± differential pair (Serial Digital Video red
output)
DDI for HDMI/DVI: TMDS1_DATA lanes 2 differential pairs
I PCIE
O PCIE
AC coupled off Module
PEG channel 15, Transmit Output differential pair.
PCI Express Graphics transmit differential pairs 12
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 11
Pin Types
I Input to the Module
O Output from the Module
I/O Bi-directional input / output signal
OD Open drain output
RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.
AC coupled off Module
DDI for SDVO: SDVO1_FLDSTALL± differential pair
(Serial Digital Video Field Stall input differential pair.)
O PCIE
O PCIE
AC coupled off Module
I PCIE
I PCIE
AC coupled off Module
DDI for SDVO: SDVO1_TVCLKIN± differential pair
(Serial Digital Video TVOUT synchronization clock input differential
pair.)
AC coupled off Module
PCIe channel 4. Receive Input differential pair.
PCIe channel 5. Transmit Output differential pair.
PCIe channel 6. Transmit Output differential pair.
PCIe channel 6. Receive Input differential pair.
PCIe channel 7. Transmit Output differential pair.
PCIe channel 7. Receive Input differential pair.
PCIe Reference Clock for all COM Express PCIe lanes, and for
PEG lanes.
PEG channel 15, Receive Input differential pair.
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
Serial ATA channel 2
Transmit output differential pair.
O PCIE
AC coupled on Module
O LVDS
LVDS
O PCIE
I PCIE
AC coupled off Module
LVDS
O LVDS
LVDS
Additional receive signal differential pairs for the SuperSpeed USB
data path.
Additional receive signal differential pairs for the SuperSpeed USB
data path.
LVDS Signals and Descriptions
O LVDS
LVDS
EDP: AC coupled off
Module
LVDS channel A differential signal pair 0
eDP lane 2, TX
±
differential signal pair
LVDS Channel A differential pairs
Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-,
LVDS_B[0:3]+/-. LV/-, LV/-) shall have 100
Ω
terminations across the pairs at the destination. These terminations
may be on the Carrier Board if the Carrier Board implements a LVDS
deserializer on-board.
eDP: eDP differential pairs
O LVDS
LVDS channel A differential signal pair 1
eDP lane 1, TX
±
differential signal pair
O LVDS
LVDS
EDP: AC coupled off
Module
LVDS channel A differential signal pair 3
LVDS
EDP: AC coupled off
Module
LVDS channel A differential signal pair 2
eDP lane 0, TX
±
differential signal pair
O LVDS
LVDS
EDP: AC coupled off
Module
LVDS channel B differential signal pair 2
LVDS Channel A differential clock
O LVDS
LVDS
LVDS channel A differential clock pair
eDP lane 3, TX
±
differential pair
O LVDS
LVDS channel B differential signal pair 0
LPC multiplexed command, address and data.
LPC encoded DMA/Bus master request.
SPI Signals and Descriptions
LVDS channel B differential signal pair 1
LVDS Channel B differential clock
LVDS Channel B differential pairs
Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-,
LVDS_B[0:3]+/-. LV/-, LV/-) shall have 100
Ω
terminations across the pairs at the destination. These terminations
may be on the Carrier Board if the Carrier Board implements a LVDS
deserializer on-board.
3.3V / 3.3V
LPC serial DMA request
AC coupled off Module
DDI for SDVO: SDVO1_INT± differential pair
(Serial Digital Video B interrupt input differential pair)
O LVDS
LVDS
LVDS channel B differential signal pair 3
O LVDS
LVDS
LVDS channel B differential clock pair
I/O CMOS
3.3V / 3.3V
VGA Signals and Descriptions
NA
Selection straps to determine the BIOS boot device.
The Carrier should only float these or pull them low, please refer to
COM Express Module Base Specification Revision 2.1 for strapping
options of BIOS disable signals.
LPC Signals and Descriptions
I CMOS
I CMOS
LPC multiplexed address, command and data bus.
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 2
I/O USB
Additional transmit signal differential pairs for the SuperSpeed USB
data path.
AC coupled on Module
Additional transmit signal differential pairs for the SuperSpeed USB
data path.
I PCIE
AC coupled off Module
Additional receive signal differential pairs for the SuperSpeed USB
data path.
O PCIE
AC coupled on Module
Additional transmit signal differential pairs for the SuperSpeed USB
data path.
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
Additional transmit signal differential pairs for the SuperSpeed USB
data path.
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 6
Additional receive signal differential pairs for the SuperSpeed USB
data path.
I PCIE
AC coupled off Module
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 5
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 7.
USB7 may be configured as a USB client or as a host, or both, at the
Module designer's discretion. (KH960 default set as a host)
3.3V Suspend/3.3V
USB differential pairs, channel 4
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 3
I/O USB
PEG channel 12, Transmit Output differential pair.
3.3V Suspend/3.3V
USB differential pairs, channel 1
O PCIE
AC coupled off Module
DDI Signals Descriptions
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 14
PCI Express Graphics receive differential pairs 12
ExpressCard Signals and Descriptions
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 14
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 15
PEG channel 12, Receive Input differential pair.
PEG channel 13 Transmit Output differential pair.
PEG channel 13, Receive Input differential pair.
USB Signals and Descriptions
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 0
PEG channel 14, Transmit Output differential pair.
PEG channel 14, Receive Input differential pair.
PEG channel 9, Transmit Output differential pair.
PEG channel 9, Receive Input differential pair.
PEG channel 10, Transmit Output differential pair.
O PCIE
AC coupled on Module
PCI Express Graphics receive differential pairs 13
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 15
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 13
AC coupled off Module
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 11
PCI Express Graphics receive differential pairs 10
PEG channel 10, Receive Input differential pair.
PEG channel 11, Transmit Output differential pair.
PEG channel 11, Receive Input differential pair.
O PCIE
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 6
PCI Express Graphics transmit differential pairs 10
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 9
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 9
PEG channel 5, Receive Input differential pair.
PEG channel 6, Transmit Output differential pair.
PEG channel 6, Receive Input differential pair.
PEG channel 7, Transmit Output differential pair.
PEG channel 7, Receive Input differential pair.
PEG channel 8, Transmit Output differential pair.
O PCIE
AC coupled on Module
PCI Express Graphics receive differential pairs 8
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 7
AC coupled on Module
PCI Express Graphics transmit differential pairs 7
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 6
PEG channel 8, Receive Input differential pair.
I PCIE
AC coupled off Module
PCI Express Graphics transmit differential pairs 8
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 5
PEG channel 5, Transmit Output differential pair.
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 4
I PCIE
AC coupled off Module
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 3
PCI Express Graphics transmit differential pairs 5
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 2
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 3
PCI Express Graphics receive differential pairs 4
O PCIE
AC coupled on Module
PEG channel 2, Receive Input differential pair.
PEG channel 3, Transmit Output differential pair.
PEG channel 3, Receive Input differential pair.
PEG channel 4, Transmit Output differential pair.
PEG channel 4, Receive Input differential pair.
PCI Express Graphics transmit differential pairs 2
PEG Signals and Descriptions
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 0
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 0
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 1
AC coupled off Module
PCI Express Graphics receive differential pairs 1
PEG channel 0, Transmit Output differential pair.
PEG channel 0, Receive Input differential pair.
PEG channel 1, Transmit Output differential pair.
PEG channel 1, Receive Input differential pair.
PEG channel 2, Transmit Output differential pair.
O PCIE
AC coupled on Module
I PCIE
PCI Express Differential Receive Pairs 7
O PCIE
PCIE
Reference clock output for all PCI Express and PCI Express Graphics
lanes.
PCI Express Differential Receive Pairs 6
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 7
PCI Express Differential Transmit Pairs 4
PCIe channel 5. Receive Input differential pair.
PCIe channel 4. Transmit Output differential pair.
I PCIE
AC coupled off Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 6
I PCIE
AC coupled off Module
PCI Express Differential Receive Pairs 5
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 5
PCI Express Differential Receive Pairs 4
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
PCIe channel 3. Receive Input differential pair.
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 1
PCI Express Differential Receive Pairs 1
PCI Express Differential Receive Pairs 3
I PCIE
AC coupled off Module
PCI Express Differential Receive Pairs 2
PCI Express Differential Transmit Pairs 3
O PCIE
AC coupled on Module
PCIe channel 3. Transmit Output differential pair.
PCIe channel 2. Transmit Output differential pair.
PCIe channel 2. Receive Input differential pair.
PCIe channel 1. Transmit Output differential pair.
PCIe channel 1. Receive Input differential pair.
I PCIE
AC coupled off Module
Serial ATA channel 0
Transmit output differential pair.
Serial ATA channel 0
Receive input differential pair.
Serial ATA channel 1
Transmit output differential pair.
Serial ATA channel 3
Receive input differential pair.
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 0
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 2
I PCIE
AC coupled off Module
I PCIE
AC coupled off Module
PCI Express Differential Receive Pairs 0
Serial ATA channel 2
Receive input differential pair.
Serial ATA channel 3
Transmit output differential pair.
PCIe channel 0. Transmit Output differential pair.
PCIe channel 0. Receive Input differential pair.
DDI for Display Port: DP1_LANE 1 differential pairs
DDI for SDVO: SDVO1_GRN± differential pair (Serial Digital Video
green output)
DDI for HDMI/DVI: TMDS1_DATA lanes 1 differential pairs
DDI for Display Port: DP1_LANE 2 differential pairs
DDI for SDVO: SDVO1_BLU± differential pair (Serial Digital Video blue
output)
DDI for HDMI/DVI: TMDS1_DATA lanes 0 differential pairs
DDI for Display Port: DP1_LANE 3 differential pairs
DDI for SDVO: SDVO1_CK± differential pair (Serial Digital Video clock
output)
DDI for HDMI/DVI: TMDS1_CLK differential pairs
AC97/HDA Signals and Descriptions
Serial TDM data inputs from up to 3 CODECs.
Gigabit Ethernet Signals and Descriptions
PCI Express Lanes Signals and Descriptions
Serial ATA or SAS Channel 0 transmit differential pair.
Serial ATA or SAS Channel 0 receive differential pair.
Serial ATA or SAS Channel 3 transmit differential pair.
Serial ATA or SAS Channel 3 receive differential pair.
Serial ATA or SAS Channel 2 receive differential pair.
Serial ATA or SAS Channel 2 transmit differential pair.
Gigabit Ethernet Controller 0: Media Dependent Interface Differential
Pairs 0,1,2,3. The MDI can operate in 1000, 100 and 10 Mbit / sec
modes. Some pairs are unused in some modes, per the following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/-
MDI[3]+/- B1_DD+/-
Serial ATA or SAS Channel 1 receive differential pair.
SATA Signals and Descriptions
Serial ATA or SAS Channel 1 transmit differential pair.
Audio Serial Data Input Stream from CODEC[0:2].
Media Dependent Interface (MDI) differential pair 0.
Media Dependent Interface (MDI) differential pair 1.
Media Dependent Interface (MDI) differential pair 2.
Only used for 1000Mbit/sec Gigabit Ethernet mode.
Media Dependent Interface (MDI) differential pair 3.
Only used for 1000Mbit/sec Gigabit Ethernet mode.
Serial ATA channel 1
Receive input differential pair.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
AC/HDA_RST#
A30
O CMOS
3.3V Suspend/3.3V
series 33
Ω
resistor
Reset output to CODEC, active low.
CODEC Reset.
AC/HDA_SYNC
A29
O CMOS
3.3V/3.3V
series 33
Ω
resistor
Sample-synchronization signal to the CODEC(s).
Serial Sample Rate Synchronization.
AC/HDA_BITCLK
A32
I/O CMOS
3.3V/3.3V
series 33
Ω
resistor
Serial data clock generated by the external CODEC(s).
24 MHz Serial Bit Clock for HDA CODEC.
AC/HDA_SDOUT
A33
O CMOS
3.3V/3.3V
series 33
Ω
resistor
Serial TDM data output to the CODEC.
Audio Serial Data Output Stream.
AC/HDA_SDIN0
B30
I/O CMOS
3.3V Suspend/3.3V
AC/HDA_SDIN1
B29
I/O CMOS
3.3V Suspend/3.3V
AC/HDA_SDIN2
B28
I/O CMOS
3.3V Suspend/3.3V
NC
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
GB
A13
I/O Analog
3.3V max Suspend
GBE0_MDI0-
A12
I/O Analog
3.3V max Suspend
GB
A10
I/O Analog
3.3V max Suspend
GBE0_MDI1-
A9
I/O Analog
3.3V max Suspend
GB
A7
I/O Analog
3.3V max Suspend
GBE0_MDI2-
A6
I/O Analog
3.3V max Suspend
GB
A3
I/O Analog
3.3V max Suspend
GBE0_MDI3-
A2
I/O Analog
3.3V max Suspend
GBE0_ACT#
B2
OD CMOS
3.3V Suspend/3.3V
Gigabit Ethernet Controller 0 activity indicator, active low.
Ethernet controller 0 activity indicator, active low.
GBE0_LINK#
A8
OD CMOS
3.3V Suspend/3.3V
Gigabit Ethernet Controller 0 link indicator, active low.
Ethernet controller 0 link indicator, active low.
GBE0_LINK100#
A4
OD CMOS
3.3V Suspend/3.3V
Gigabit Ethernet Controller 0 100 Mbit / sec link indicator, active low.
Ethernet controller 0 100Mbit/sec link indicator, active low.
GBE0_LINK1000#
A5
OD CMOS
3.3V Suspend/3.3V
Gigabit Ethernet Controller 0 1000 Mbit / sec link indicator, active low. Ethernet controller 0 1000Mbit/sec link indicator, active low.
GBE0_CTREF
A14
REF
GND min 3.3V max
NC
Reference voltage for Carrier Board Ethernet channel 0 magnetics
center
tap. The reference voltage is determined by the requirements of the
Module PHY and may be as low as 0V and as high as 3.3V.
The reference voltage output shall be current limited on the Module.
In
Reference voltage for Carrier Board Ethernet channel 0
magnetics center tap.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
S
A16
O SATA
AC coupled on Module
AC Coupling capacitor
SATA0_TX-
A17
O SATA
AC coupled on Module
AC Coupling capacitor
S
A19
I SATA
AC coupled on Module
AC Coupling capacitor
SATA0_RX-
A20
I SATA
AC coupled on Module
AC Coupling capacitor
S
B16
O SATA
AC coupled on Module
AC Coupling capacitor
SATA1_TX-
B17
O SATA
AC coupled on Module
AC Coupling capacitor
S
B19
I SATA
AC coupled on Module
AC Coupling capacitor
SATA1_RX-
B20
I SATA
AC coupled on Module
AC Coupling capacitor
S
A22
O SATA
AC coupled on Module
AC Coupling capacitor
SATA2_TX-
A23
O SATA
AC coupled on Module
AC Coupling capacitor
S
A25
I SATA
AC coupled on Module
AC Coupling capacitor
SATA2_RX-
A26
I SATA
AC coupled on Module
AC Coupling capacitor
S
B22
O SATA
AC coupled on Module
AC Coupling capacitor
SATA3_TX-
B23
O SATA
AC coupled on Module
AC Coupling capacitor
S
B25
I SATA
AC coupled on Module
AC Coupling capacitor
SATA3_RX-
B26
I SATA
AC coupled on Module
AC Coupling capacitor
(S)ATA_ACT#
A28
I/O CMOS
3.3V / 3.3V
PU 10K
to 3.3V
ATA (parallel and serial) or SAS activity indicator, active low.
Serial ATA activity LED. Open collector output pin driven during
SATA command activity.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
P
A68
AC Coupling capacitor
PCIE_TX0-
A69
AC Coupling capacitor
P
B68
PCIE_RX0-
B69
P
A64
AC Coupling capacitor
PCIE_TX1-
A65
AC Coupling capacitor
P
B64
PCIE_RX1-
B65
P
A61
AC Coupling capacitor
PCIE_TX2-
A62
AC Coupling capacitor
P
B61
PCIE_RX2-
B62
P
A58
AC Coupling capacitor
PCIE_TX3-
A59
AC Coupling capacitor
P
B58
PCIE_RX3-
B59
P
A55
AC Coupling capacitor
PCIE_TX4-
A56
AC Coupling capacitor
P
B55
PCIE_RX4-
B56
P
A52
AC Coupling capacitor
PCIE_TX5-
A53
AC Coupling capacitor
P
B52
PCIE_RX5-
B53
P
D19
AC Coupling capacitor
PCIE_TX6-
D20
AC Coupling capacitor
P
C19
PCIE_RX6-
C20
P
D22
AC Coupling capacitor
PCIE_TX7-
D23
AC Coupling capacitor
P
C22
PCIE_RX7-
C23
PCIE_
A88
PCIE_CLK_REF-
A89
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
D52
AC Coupling capacitor
PEG_TX0-
D53
AC Coupling capacitor
C52
PEG_RX0-
C53
D55
AC Coupling capacitor
PEG_TX1-
D56
AC Coupling capacitor
C55
PEG_RX1-
C56
D58
AC Coupling capacitor
PEG_TX2-
D59
AC Coupling capacitor
C58
PEG_RX2-
C59
D61
AC Coupling capacitor
PEG_TX3-
D62
AC Coupling capacitor
C61
PEG_RX3-
C62
D65
AC Coupling capacitor
PEG_TX4-
D66
AC Coupling capacitor
C65
PEG_RX4-
C66
D68
AC Coupling capacitor
PEG_TX5-
D69
AC Coupling capacitor
C68
PEG_RX5-
C69
D71
AC Coupling capacitor
PEG_TX6-
D72
AC Coupling capacitor
C71
PEG_RX6-
C72
D74
AC Coupling capacitor
PEG_TX7-
D75
AC Coupling capacitor
C74
PEG_RX7-
C75
D78
AC Coupling capacitor
PEG_TX8-
D79
AC Coupling capacitor
C78
PEG_RX8-
C79
D81
AC Coupling capacitor
PEG_TX9-
D82
AC Coupling capacitor
C81
PEG_RX9-
C82
P
D85
AC Coupling capacitor
PEG_TX10-
D86
AC Coupling capacitor
P
C85
PEG_RX10-
C86
P
D88
AC Coupling capacitor
PEG_TX11-
D89
AC Coupling capacitor
P
C88
PEG_RX11-
C89
P
D91
AC Coupling capacitor
PEG_TX12-
D92
AC Coupling capacitor
P
C91
PEG_RX12-
C92
P
D94
AC Coupling capacitor
PEG_TX13-
D95
AC Coupling capacitor
P
C94
PEG_RX13-
C95
P
D98
AC Coupling capacitor
PEG_TX14-
D99
AC Coupling capacitor
P
C98
PEG_RX14-
C99
P
D101
AC Coupling capacitor
PEG_TX15-
D102
AC Coupling capacitor
P
C101
PEG_RX15-
C102
PEG_LANE_RV#
D54
I CMOS
3.3V / 3.3V
PU 10K
Ω
to 3V3
PCI Express Graphics lane reversal input strap.
Pull low on the Carrier board to reverse lane order.
PCI Express Graphics lane reversal input strap.
Pull low on the carrier board to reverse lane order.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
EXCD0_CPPE#
A49
I CMOS
3.3V /3.3V
PU 10k to 3.3V
PCI ExpressCard: PCI Express capable card request, active low, one
per card
PCI ExpressCard0: PCI Express capable card request, active low,
one per card
EXCD0_PERST#
A48
O CMOS
3.3V /3.3V
PCI ExpressCard: reset, active low, one per card
PCI ExpressCard0: reset, active low, one per card
EXCD1_CPPE#
B48
I CMOS
3.3V /3.3V
PU 10k to 3.3V
PCI ExpressCard: PCI Express capable card request, active low, one
percard
PCI ExpressCard1: PCI Express capable card request, active low,
one per card
EXCD1_PERST#
B47
O CMOS
3.3V /3.3V
PCI ExpressCard: reset, active low, one per card
PCI ExpressCard1: reset, active low, one per card
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
USB0+
A46
USB Port 0, data + or D+
USB0-
A45
USB Port 0, data - or D-
USB1+
B46
USB Port 1, data + or D+
USB1-
B45
USB Port 1, data - or D-
USB2+
A43
USB Port 2, data + or D+
USB2-
A42
USB Port 2, data - or D-
USB3+
B43
USB Port 3, data + or D+
USB3-
B42
USB Port 3, data - or D-
USB4+
A40
USB Port 4, data + or D+
USB4-
A39
USB Port 4, data - or D-
USB5+
B40
USB Port 5, data + or D+
USB5-
B39
USB Port 5, data - or D-
USB6+
A37
USB Port 6, data + or D+
USB6-
A36
USB Port 6, data - or D-
USB7+
B37
USB Port 7, data + or D+
USB7-
B36
USB Port 7, data - or D-
USB_0_1_OC#
B44
I CMOS
3.3V Suspend/3.3V
PU 10K
to 3.3V
Suspend
USB over-current sense, USB channels 0 and 1. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
USB over-current sense, USB ports 0 and 1.
USB_2_3_OC#
A44
I CMOS
3.3V Suspend/3.3V
PU 10K
to 3.3V
Suspend
USB over-current sense, USB channels 2 and 3. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
USB over-current sense, USB ports 2 and 3.
USB_4_5_OC#
B38
I CMOS
3.3V Suspend/3.3V
PU 10K
to 3.3V
Suspend
USB over-current sense, USB channels 4 and 5. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
USB over-current sense, USB ports 4 and 5.
USB_6_7_OC#
A38
I CMOS
3.3V Suspend/3.3V
PU 10K
to 3.3V
Suspend
USB over-current sense, USB channels 6 and 7. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
USB over-current sense, USB ports 6 and 7.
US
D4
AC Coupling capacitor
USB Port 0, SuperSpeed TX +
USB_SSTX0-
D3
AC Coupling capacitor
USB Port 0, SuperSpeed TX -
US
C4
USB Port 0, SuperSpeed RX +
USB_SSRX0-
C3
USB Port 0, SuperSpeed RX -
US
D7
AC Coupling capacitor
USB Port 1, SuperSpeed TX +
USB_SSTX1-
D6
AC Coupling capacitor
USB Port 1, SuperSpeed TX -
US
C7
USB Port 1, SuperSpeed RX +
USB_SSRX1-
C6
USB Port 1, SuperSpeed RX -
US
D10
AC Coupling capacitor
USB Port 2, SuperSpeed TX +
USB_SSTX2-
D9
AC Coupling capacitor
USB Port 2, SuperSpeed TX -
US
C10
USB Port 2, SuperSpeed RX +
USB_SSRX2-
C9
USB Port 2, SuperSpeed RX -
US
D13
AC Coupling capacitor
USB Port 3, SuperSpeed TX +
USB_SSTX3-
D12
AC Coupling capacitor
USB Port 3, SuperSpeed TX -
US
C13
USB Port 3, SuperSpeed RX +
USB_SSRX3-
C12
USB Port 3, SuperSpeed RX -
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
/
A71
LVDS_A0-/eDP_TX2-
A72
/
A73
LVDS_A1-/eDP_TX1-
A74
/
A75
LVDS_A2-/eDP_TX0-
A76
A78
LVDS_A3-
A79
LV/
A81
LVDS_A_CK-/eDP_TX3-
A82
B71
LVDS_B0-
B72
B73
LVDS_B1-
B74
B75
LVDS_B2-
B76
B77
LVDS_B3-
B78
LV
B81
LVDS_B_CK-
B82
LVDS_VDD_EN/eDP_VDD_EN
A77
O CMOS
3.3V / 3.3V
LVDS panel / eDP power enable
LVDS flat panel power enable.
eDP power enable
LVDS_BKLT_EN/eDP_BKLT_EN
B79
O CMOS
3.3V / 3.3V
LVDS panel / eDP backlight enable
LVDS flat panel backlight enable high active signal
eDP backlight enable
LVDS_BKLT_CTRL/eDP_BKLT_CTRL
B83
O CMOS
3.3V / 3.3V
PD 100K
to GND
LVDS panel / eDP backlight brightness control
LVDS flat panel backlight brightness control
EDP backlight brightness control
LVDS_I2C_CK/
A83
I/O OD CMOS
3.3V / 3.3V
PU 2.2K
to 3.3V
I2C clock output for LVDS display use / eDP AUX+
DDC I2C clock signal used for flat panel detection and control.
eDP auxiliary lane +
LVDS_I2C_DAT/eDP_AUX-
A84
I/O OD CMOS
3.3V / 3.3V
PU 2.2K
to 3.3V
I2C data line for LVDS display use / eDP AUX-
DDC I2C data signal used for flat panel detection and control.
eDP auxiliary lane -
RSVD/eDP_HPD
A87
I CMOS
3.3V / 3.3V
RSV PD 100K
Ω
to GND
eDP_HPD:Detection of Hot Plug / Unplug and notification of the link
layer
eDP_HPD: Detection of Hot Plug / Unplug and notification of the
link layer
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
LPC_AD0
B4
LPC_AD1
B5
LPC_AD2
B6
LPC_AD3
B7
LPC_FRAME#
B3
O CMOS
3.3V / 3.3V
LPC frame indicates the start of an LPC cycle
LPC frame indicates start of a new cycle or termination of a
broken cycle.
LPC_DRQ0#
B8
PU 10K to 3.3V, not
support.
LPC_DRQ1#
B9
PU 10K to 3.3V, not
support.
LPC_SERIRQ
A50
I/O CMOS
3.3V / 3.3V
PU 10K to 3.3V
LPC serial interrupt
LPC serialized IRQ.
LPC_CLK
B10
O CMOS
3.3V / 3.3V
series 22
Ω
resistor
LPC clock output - 33MHz nominal
LPC clock output 33MHz.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
SPI_CS#
B97
O CMOS
3.3V Suspend/3.3V
Chip select for Carrier Board SPI - may be sourced from chipset SPI0 or
SPI1
Chip select for Carrier Board SPI – may be sourced from chipset
SPI0 or SPI1
SPI_MISO
A92
I CMOS
3.3V Suspend/3.3V
Data in to Module from Carrier SPI
Data in to Module from Carrier SPI
SPI_MOSI
A95
O CMOS
3.3V Suspend/3.3V
Data out from Module to Carrier SPI
Data out from Module to Carrier SPI
SPI_CLK
A94
O CMOS
3.3V Suspend/3.3V
Clock from Module to Carrier SPI
Clock from Module to Carrier SPI
SPI_POWER
A91
O
3.3V Suspend/3.3V
Power supply for Carrier Board SPI – sourced from Module – nominally
3.3V. The Module shall provide a minimum of 100mA on SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER. SPI_POWER
shall only be used to power SPI devices on the Carrier Board.
Power supply for Carrier Board SPI – sourced from Module –
nominally 3.3V. The Module shall provide a minimum of 100mA
on SPI_POWER. Carriers shall use less than 100mA of
SPI_POWER. SPI_POWER shall only be used to power SPI
devices on the Carrier.
BIOS_DIS0#
A34
PU 10K
Ω
to 3V3 Suspend.
Selection strap to determine the BIOS boot device.
The Carrier should only float these or pull them low, please refer
to for strapping options of BIOS disable signals.
BIOS_DIS1#
B88
PU 10K
Ω
to 3V3 Suspend.
Selection strap to determine the BIOS boot device.
The Carrier should only float these or pull them low.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
VGA_RED
B89
O Analog
Analog
PD 150
to GND
Red for monitor. Analog DAC output, designed to drive a 37.5
Ω
equivalent load.
Red component of analog DAC monitor output, designed to drive
a 37.5
Ω
equivalent load.
VGA_GRN
B91
O Analog
Analog
PD 150
to GND
Green for monitor. Analog DAC output, designed to drive a 37.5
Ω
equivalent load.
Green component of analog DAC monitor output, designed to
drive a 37.5
Ω
equivalent load.
VGA_BLU
B92
O Analog
Analog
PD 150
to GND
Blue for monitor. Analog DAC output, designed to drive a 37.5
Ω
equivalent load.
Blue component of analog DAC monitor output, designed to
drive a 37.5
Ω
equivalent load.
VGA_HSYNC
B93
O CMOS
3.3V / 3.3V
Horizontal sync output to VGA monitor
Horizontal sync output to VGA monitor.
VGA_VSYNC
B94
O CMOS
3.3V / 3.3V
Vertical sync output to VGA monitor
Vertical sync output to VGA monitor.
VGA_I2C_CK
B95
I/O OD CMOS
3.3V / 3.3V
PU 2.2K
to 3.3V
DDC clock line (I2C port dedicated to identify VGA monitor
capabilities)
DDC clock line (I2C port dedicated to identify VGA monitor
capabilities).
VGA_I2C_DAT
B96
I/O OD CMOS
3.3V / 3.3V
PU 2.2K
to 3.3V
DDC data line.
DDC data line.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
KH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
DDI
D26
DP for DP / TMDS for HDMI or DVI
DDI1_PAIR0-
D27
DP1_LANE0- for DP / TMDS1_DATA2- for HDMI or DVI
DDI
D29
DP for DP / TMDS for HDMI or DVI
DDI1_PAIR1-
D30
DP1_LANE1- for DP / TMDS1_DATA1- for HDMI or DVI
DDI
D32
DP for DP / TMDS for HDMI or DVI
DDI1_PAIR2-
D33
DP1_LANE2- for DP / TMDS1_DATA0- for HDMI or DVI
DDI
D36
DP for DP / TM
DDI1_PAIR3-
D37
DP1_LANE3- for DP / TMDS1_CLK-
DDI
C25
NC
NA
DDI1_PAIR4-
C26
NC
NA
DDI
C29
NC
NA
DDI1_PAIR5-
C30
NC
NA
DDI
C15
NC
NA
DDI1_PAIR6-
C16
NC
NA
I PCIE
DDI for Display Port: DP1_LANE 0 differential pairs
DDI for SDVO: SDVO1_RED± differential pair (Serial Digital Video red
output)
DDI for HDMI/DVI: TMDS1_DATA lanes 2 differential pairs
I PCIE
O PCIE
AC coupled off Module
PEG channel 15, Transmit Output differential pair.
PCI Express Graphics transmit differential pairs 12
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 11
Pin Types
I Input to the Module
O Output from the Module
I/O Bi-directional input / output signal
OD Open drain output
RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.
AC coupled off Module
DDI for SDVO: SDVO1_FLDSTALL± differential pair
(Serial Digital Video Field Stall input differential pair.)
O PCIE
O PCIE
AC coupled off Module
I PCIE
I PCIE
AC coupled off Module
DDI for SDVO: SDVO1_TVCLKIN± differential pair
(Serial Digital Video TVOUT synchronization clock input differential
pair.)
AC coupled off Module
PCIe channel 4. Receive Input differential pair.
PCIe channel 5. Transmit Output differential pair.
PCIe channel 6. Transmit Output differential pair.
PCIe channel 6. Receive Input differential pair.
PCIe channel 7. Transmit Output differential pair.
PCIe channel 7. Receive Input differential pair.
PCIe Reference Clock for all COM Express PCIe lanes, and for
PEG lanes.
PEG channel 15, Receive Input differential pair.
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
Serial ATA channel 2
Transmit output differential pair.
O PCIE
AC coupled on Module
O LVDS
LVDS
O PCIE
I PCIE
AC coupled off Module
LVDS
O LVDS
LVDS
Additional receive signal differential pairs for the SuperSpeed USB
data path.
Additional receive signal differential pairs for the SuperSpeed USB
data path.
LVDS Signals and Descriptions
O LVDS
LVDS
EDP: AC coupled off
Module
LVDS channel A differential signal pair 0
eDP lane 2, TX
±
differential signal pair
LVDS Channel A differential pairs
Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-,
LVDS_B[0:3]+/-. LV/-, LV/-) shall have 100
Ω
terminations across the pairs at the destination. These terminations
may be on the Carrier Board if the Carrier Board implements a LVDS
deserializer on-board.
eDP: eDP differential pairs
O LVDS
LVDS channel A differential signal pair 1
eDP lane 1, TX
±
differential signal pair
O LVDS
LVDS
EDP: AC coupled off
Module
LVDS channel A differential signal pair 3
LVDS
EDP: AC coupled off
Module
LVDS channel A differential signal pair 2
eDP lane 0, TX
±
differential signal pair
O LVDS
LVDS
EDP: AC coupled off
Module
LVDS channel B differential signal pair 2
LVDS Channel A differential clock
O LVDS
LVDS
LVDS channel A differential clock pair
eDP lane 3, TX
±
differential pair
O LVDS
LVDS channel B differential signal pair 0
LPC multiplexed command, address and data.
LPC encoded DMA/Bus master request.
SPI Signals and Descriptions
LVDS channel B differential signal pair 1
LVDS Channel B differential clock
LVDS Channel B differential pairs
Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-,
LVDS_B[0:3]+/-. LV/-, LV/-) shall have 100
Ω
terminations across the pairs at the destination. These terminations
may be on the Carrier Board if the Carrier Board implements a LVDS
deserializer on-board.
3.3V / 3.3V
LPC serial DMA request
AC coupled off Module
DDI for SDVO: SDVO1_INT± differential pair
(Serial Digital Video B interrupt input differential pair)
O LVDS
LVDS
LVDS channel B differential signal pair 3
O LVDS
LVDS
LVDS channel B differential clock pair
I/O CMOS
3.3V / 3.3V
VGA Signals and Descriptions
NA
Selection straps to determine the BIOS boot device.
The Carrier should only float these or pull them low, please refer to
COM Express Module Base Specification Revision 2.1 for strapping
options of BIOS disable signals.
LPC Signals and Descriptions
I CMOS
I CMOS
LPC multiplexed address, command and data bus.
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 2
I/O USB
Additional transmit signal differential pairs for the SuperSpeed USB
data path.
AC coupled on Module
Additional transmit signal differential pairs for the SuperSpeed USB
data path.
I PCIE
AC coupled off Module
Additional receive signal differential pairs for the SuperSpeed USB
data path.
O PCIE
AC coupled on Module
Additional transmit signal differential pairs for the SuperSpeed USB
data path.
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
Additional transmit signal differential pairs for the SuperSpeed USB
data path.
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 6
Additional receive signal differential pairs for the SuperSpeed USB
data path.
I PCIE
AC coupled off Module
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 5
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 7.
USB7 may be configured as a USB client or as a host, or both, at the
Module designer's discretion. (KH960 default set as a host)
3.3V Suspend/3.3V
USB differential pairs, channel 4
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 3
I/O USB
PEG channel 12, Transmit Output differential pair.
3.3V Suspend/3.3V
USB differential pairs, channel 1
O PCIE
AC coupled off Module
DDI Signals Descriptions
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 14
PCI Express Graphics receive differential pairs 12
ExpressCard Signals and Descriptions
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 14
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 15
PEG channel 12, Receive Input differential pair.
PEG channel 13 Transmit Output differential pair.
PEG channel 13, Receive Input differential pair.
USB Signals and Descriptions
I/O USB
3.3V Suspend/3.3V
USB differential pairs, channel 0
PEG channel 14, Transmit Output differential pair.
PEG channel 14, Receive Input differential pair.
PEG channel 9, Transmit Output differential pair.
PEG channel 9, Receive Input differential pair.
PEG channel 10, Transmit Output differential pair.
O PCIE
AC coupled on Module
PCI Express Graphics receive differential pairs 13
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 15
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 13
AC coupled off Module
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 11
PCI Express Graphics receive differential pairs 10
PEG channel 10, Receive Input differential pair.
PEG channel 11, Transmit Output differential pair.
PEG channel 11, Receive Input differential pair.
O PCIE
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 6
PCI Express Graphics transmit differential pairs 10
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 9
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 9
PEG channel 5, Receive Input differential pair.
PEG channel 6, Transmit Output differential pair.
PEG channel 6, Receive Input differential pair.
PEG channel 7, Transmit Output differential pair.
PEG channel 7, Receive Input differential pair.
PEG channel 8, Transmit Output differential pair.
O PCIE
AC coupled on Module
PCI Express Graphics receive differential pairs 8
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 7
AC coupled on Module
PCI Express Graphics transmit differential pairs 7
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 6
PEG channel 8, Receive Input differential pair.
I PCIE
AC coupled off Module
PCI Express Graphics transmit differential pairs 8
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 5
PEG channel 5, Transmit Output differential pair.
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 4
I PCIE
AC coupled off Module
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 3
PCI Express Graphics transmit differential pairs 5
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 2
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 3
PCI Express Graphics receive differential pairs 4
O PCIE
AC coupled on Module
PEG channel 2, Receive Input differential pair.
PEG channel 3, Transmit Output differential pair.
PEG channel 3, Receive Input differential pair.
PEG channel 4, Transmit Output differential pair.
PEG channel 4, Receive Input differential pair.
PCI Express Graphics transmit differential pairs 2
PEG Signals and Descriptions
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 0
I PCIE
AC coupled off Module
PCI Express Graphics receive differential pairs 0
O PCIE
AC coupled on Module
PCI Express Graphics transmit differential pairs 1
AC coupled off Module
PCI Express Graphics receive differential pairs 1
PEG channel 0, Transmit Output differential pair.
PEG channel 0, Receive Input differential pair.
PEG channel 1, Transmit Output differential pair.
PEG channel 1, Receive Input differential pair.
PEG channel 2, Transmit Output differential pair.
O PCIE
AC coupled on Module
I PCIE
PCI Express Differential Receive Pairs 7
O PCIE
PCIE
Reference clock output for all PCI Express and PCI Express Graphics
lanes.
PCI Express Differential Receive Pairs 6
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 7
PCI Express Differential Transmit Pairs 4
PCIe channel 5. Receive Input differential pair.
PCIe channel 4. Transmit Output differential pair.
I PCIE
AC coupled off Module
I PCIE
AC coupled off Module
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 6
I PCIE
AC coupled off Module
PCI Express Differential Receive Pairs 5
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 5
PCI Express Differential Receive Pairs 4
O PCIE
AC coupled on Module
I PCIE
AC coupled off Module
PCIe channel 3. Receive Input differential pair.
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 1
PCI Express Differential Receive Pairs 1
PCI Express Differential Receive Pairs 3
I PCIE
AC coupled off Module
PCI Express Differential Receive Pairs 2
PCI Express Differential Transmit Pairs 3
O PCIE
AC coupled on Module
PCIe channel 3. Transmit Output differential pair.
PCIe channel 2. Transmit Output differential pair.
PCIe channel 2. Receive Input differential pair.
PCIe channel 1. Transmit Output differential pair.
PCIe channel 1. Receive Input differential pair.
I PCIE
AC coupled off Module
Serial ATA channel 0
Transmit output differential pair.
Serial ATA channel 0
Receive input differential pair.
Serial ATA channel 1
Transmit output differential pair.
Serial ATA channel 3
Receive input differential pair.
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 0
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 2
I PCIE
AC coupled off Module
I PCIE
AC coupled off Module
PCI Express Differential Receive Pairs 0
Serial ATA channel 2
Receive input differential pair.
Serial ATA channel 3
Transmit output differential pair.
PCIe channel 0. Transmit Output differential pair.
PCIe channel 0. Receive Input differential pair.
DDI for Display Port: DP1_LANE 1 differential pairs
DDI for SDVO: SDVO1_GRN± differential pair (Serial Digital Video
green output)
DDI for HDMI/DVI: TMDS1_DATA lanes 1 differential pairs
DDI for Display Port: DP1_LANE 2 differential pairs
DDI for SDVO: SDVO1_BLU± differential pair (Serial Digital Video blue
output)
DDI for HDMI/DVI: TMDS1_DATA lanes 0 differential pairs
DDI for Display Port: DP1_LANE 3 differential pairs
DDI for SDVO: SDVO1_CK± differential pair (Serial Digital Video clock
output)
DDI for HDMI/DVI: TMDS1_CLK differential pairs
AC97/HDA Signals and Descriptions
Serial TDM data inputs from up to 3 CODECs.
Gigabit Ethernet Signals and Descriptions
PCI Express Lanes Signals and Descriptions
Serial ATA or SAS Channel 0 transmit differential pair.
Serial ATA or SAS Channel 0 receive differential pair.
Serial ATA or SAS Channel 3 transmit differential pair.
Serial ATA or SAS Channel 3 receive differential pair.
Serial ATA or SAS Channel 2 receive differential pair.
Serial ATA or SAS Channel 2 transmit differential pair.
Gigabit Ethernet Controller 0: Media Dependent Interface Differential
Pairs 0,1,2,3. The MDI can operate in 1000, 100 and 10 Mbit / sec
modes. Some pairs are unused in some modes, per the following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/-
MDI[3]+/- B1_DD+/-
Serial ATA or SAS Channel 1 receive differential pair.
SATA Signals and Descriptions
Serial ATA or SAS Channel 1 transmit differential pair.
Audio Serial Data Input Stream from CODEC[0:2].
Media Dependent Interface (MDI) differential pair 0.
Media Dependent Interface (MDI) differential pair 1.
Media Dependent Interface (MDI) differential pair 2.
Only used for 1000Mbit/sec Gigabit Ethernet mode.
Media Dependent Interface (MDI) differential pair 3.
Only used for 1000Mbit/sec Gigabit Ethernet mode.
Serial ATA channel 1
Receive input differential pair.
