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Award BIOS Setup Utility
This section gives you functions to configure the system based on
the specific features of the chipset. The chipset manages bus speeds
and access to system memory resources. It also coordinates
communications between the conventional ISA bus and the PCI bus.
These items should not be altered unless necessary.
The default
settings have been chosen because they provide the best operating
conditions for your system. The only time you might consider making
any changes would be if you discovered some incompatibility or that
data was being lost while using your system.
SDRAM RAS-to-CAS Delay
This field allows you to insert a timing delay between the CAS and
RAS strobe signals, used when DRAM is written to, read from, or
refreshed. This field applies only when synchronous DRAM is installed
in the system.
SDRAM RAS Precharge Time
If there is insufficient number of cycles for the RAS to accumulate its
charge before DRAM refresh, the refresh may be incomplete and the
DRAM may fail to retain data.
SDRAM CAS Latency Time
The default setting is 3 which is 3 clock cycles for the CAS latency.
DRAM Data Integrity Mode (CB64-BX only)
The ECC (Error Checking and Correction) function is supported only
in x72 (72-bit) PC SDRAM DIMMs. If you are using x64 (64-bit) PC
SDRAM DIMMs, set this field to Non-ECC.
Non-ECC
Uses x64 PC SDRAM DIMM.
ECC
This option allows the system to recover from memory
failure. It detects single-bit and multiple-bit errors, then
automatically corrects single-bit error.
System BIOS Cacheable
When this option is enabled, accesses to the system BIOS ROM
addressed at F0000H-FFFFFH are cached, provided that the cache
controller is enabled. The larger the range of the Cache RAM, the higher
the efficiency of the system.
