8 5
3
BIOS Setup
DRAM Timing and Config
Move the cursor to this field and press <Enter>. The following
screen will appear.
The screen above list all the fields available in the DRAM Timing and Config
submenu, for ease of reference in this manual. In the actual CMOS setup, you have
to use the scroll bar to view the fields. The settings on the screen are for refer-
ence only. Your version may not be identical to this one.
CAS# Latency (Tcl)
Min RAS# Active Time (Tras)
RAS# to CAS# Delay (Trcd)
Row Precharge Time (Trp)
Row to Row Delay (Trrd)
Row Cycle Time (Trc)
Row Refresh Cyc Time (Trfc)
1T/2T Memory Timing
Read Preamble Value
Async Latency Value
DRAM Bank Interleaving
Burst Length
Enable All DIMM Clock
MTRR Mapping Mode
DRAM ECC Feature Control
x ECC Memory Interlock
x ECC MCE Enable
x Chip-Kill Mode Enable
x ECC Redirection
x DRAM Background Scrubber
x L2 Cache Background Scrubber
x Cache Background Scrubber
Phoenix - AwardBIOS CMOS Setup Utility
DRAM Timing and Config
Item Help
Menu Level
XX
↑↓→←
: Move
Enter: Select
F1: General Help
+/-/PU/PD: Value
F10: Save
ESC: Exit
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Enabled
4 beats
Disabled
Continuous
Disabled
At Least One
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
X
X
CAS Latency (Tcl)
This field is used to select the clock cycle of the CAS latency time.
The option selected specifies the timing delay before SDRAM starts
a read command after receiving it.
Min RAS# Active Time (Tras)
This field is used to select the minimum time RAS takes to read
from and write to a memory cell.
