www.dfi .com
Chapter 2 Hardware Installation
15
Chapter 2
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
BT700
Carrier Board
Description
LVDS_PPEN
111
O CMOS
3.3V/3.3V
Connect to enable control of LVDS panel power circuit
Controls panel power enable.
LVDS_BLEN
112
O CMOS
3.3V/3.3V
Connect to enable control of LVDS panel backlight power circuit.
Controls panel Backlight enable.
LVDS_BLT_CTRL/GP_PWM_OUT0
123
O CMOS
3.3V/3.3V
Connect to brightness control of LVDS panel backlight power circuit.
Primary functionality is to control the panel backlight brightness via pulse width modulation (PWM).
When not in use for this primary purpose it can be used as General Purpose PWM Output.
e
99
LVDS_A0-
eDP0_TX0-
101
e
103
LVDS_A1-
eDP0_TX1-
105
e
107
LVDS_A2-
eDP0_TX2-
109
e
113
LVDS_A3-
eDP0_TX3-
115
LVD
e
119
LVDS_A_CLK-
eDP0_AUX-
121
e
100
LVDS_B0-
eDP1_TX0-
102
e
104
LVDS_B1-
eDP1_TX1-
106
e
108
LVDS_B2-
eDP1_TX2-
110
e
114
LVDS_B3-
eDP1_TX3-
112
LVD
e
120
LVDS_B_CLK-
eDP1_AUX-
122
LVDS_DID_CLK/GP_I2C_CLK
127
I/O OD CMOS
3.3V/3.3V
PU 2.2K to 3.3V
Connect to DDC clock of LVDS panel
Primary functionality is DisplayID DDC clock line used for LVDS flat panel detection. If primary functionality is not used it can be as General Purpose I²C bus clock line.
LVDS_DID_DAT/GP_I2C_DAT
125
I/O OD CMOS
3.3V/3.3V
PU 2.2K to 3.3V
Connect to DDC clock of LVDS panel
Primary functionality DisplayID DDC data line used for LVDS flat panel detection. If primary functionality is not used it can be as General Purpose I²C bus data line.
LVDS_BLC_CLK/eDP1_HPD#
128
I/O OD CMOS
3.3V/3.3V
NC
Control clock signal for external SSC clock chip. If the primary functionality is not used, it can be used as an embedded DisplayPort secondary Hotplug detection.
LVDS_BLC_DAT/eDP0_HPD#
126
I/O OD CMOS
3.3V/3.3V
NC
Control data signal for external SSC clock chip. If the primary functionality is not used, it can be used as an embedded DisplayPort primary Hotplug detection.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
BT700
Carrier Board
Description
DP_LANE3-
133
Connect AC Coupling Capacitors 0.1uF to Device
D
131
Connect AC Coupling Capacitors 0.1uF to Device
DP_LANE2-
145
Connect AC Coupling Capacitors 0.1uF to Device
D
143
Connect AC Coupling Capacitors 0.1uF to Device
DP_LANE1-
139
Connect AC Coupling Capacitors 0.1uF to Device
D
137
Connect AC Coupling Capacitors 0.1uF to Device
DP_LANE0-
151
Connect AC Coupling Capacitors 0.1uF to Device
D
149
Connect AC Coupling Capacitors 0.1uF to Device
DP_AUX-
140
Connect AC Coupling Capacitors 0.1uF to Device, PU 100K to 3.3V
138
Connect AC Coupling Capacitors 0.1uF to Device, PD 100K to GND
DP_HDMI_HPD#
153
I CMOS
3.3V/3.3V
PU 10K to 3.3V
Hot plug detection signal that serves as an interrupt request.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
BT700
Carrier Board
Description
TMDS_CLK-
133
Connect AC Coupling Capacitors 0.1uF to Device
T
131
Connect AC Coupling Capacitors 0.1uF to Device
TMDS_LANE0-
145
Connect AC Coupling Capacitors 0.1uF to Device
TMD
143
Connect AC Coupling Capacitors 0.1uF to Device
TMDS_LANE1-
139
Connect AC Coupling Capacitors 0.1uF to Device
TMD
137
Connect AC Coupling Capacitors 0.1uF to Device
TMDS_LANE2-
151
Connect AC Coupling Capacitors 0.1uF to Device
TMD
149
Connect AC Coupling Capacitors 0.1uF to Device
HDMI_CTRL_CLK
152
I/O OD CMOS
3.3V/3.3V
PU 2.2K to 3.3V
DDC based control signal (clock) for HDMI device.
Note: Level shifters must be implemented on the carrier board for this signal in order to be compliant with the HDMI Specification.
HDMI_CTRL_DAT
150
I/O OD CMOS
3.3V/3.3V
PU 2.2K to 3.3V
DDC based control signal (data) for HDMI device.
Note: Level shifters must be implemented on the carrier board for this signal in order to be compliant with the HDMI Specification
DP_HDMI_HPD#
153
I CMOS
3.3V/3.3V
PU 10K to 3.3V
Hot plug detection signal that serves as an interrupt request.
AC coupled off Module
AC coupled off Module
AC coupled off Module
AC coupled off Module
AC coupled off Module
AC coupled off Module
AC coupled off Module
Connect to LVDS connector
Connect to LVDS connector
Connect to LVDS connector
Connect to LVDS connector
Connect to LVDS connector
Connect to LVDS connector
Connect to LVDS connector
AC coupled off Module
AC coupled off Module
HDMI Interface Signals
O TMDS
O TMDS
O TMDS
O TMDS
TMDS differential pair clock lines.
TMDS differential pair lines lane 0.
TMDS differential pair lines lane 1.
DP
DP
DP
DP
DP
LVDS secondary channel differential pair 3.
Display Port secondary channel differential pair 3.
O LVDS
LVDS secondary channel differential pair clock lines.
Display Port secondary auxiliary channel.
LVDS primary channel differential pair 3.
Display Port primary channel differential pair 3.
O LVDS
LVDS primary channel differential pair clock lines.
Display Port primary auxiliary channel.
O LVDS
LVDS secondary channel differential pair 0.
Display Port secondary channel differential pair 0.
O LVDS
LVDS secondary channel differential pair 1.
Display Port secondary channel differential pair 1.
O LVDS
LVDS secondary channel differential pair 2.
Display Port secondary channel differential pair 2.
O LVDS
LVDS
LVDS
LVDS
LVDS
O PCIE
DisplayPort differential pair lines lane 1.
O PCIE
DisplayPort differential pair lines lane 0.
O PCIE
DisplayPort differential pair lines lane 3.
O PCIE
DisplayPort differential pair lines lane 2.
DisplayPort Interface Signals
O LVDS
O LVDS
LVDS Flat Panel Signals
LVDS primary channel differential pair 0.
Display Port primary channel differential pair 0.
O LVDS
TMDS differential pair lines lane 2.
TMDS
TMDS
TMDS
TMDS
I/O PCIE
Auxiliary channel used for link management and device control. Differential pair lines.
O LVDS
LVDS primary channel differential pair 1.
Display Port primary channel differential pair 1.
LVDS primary channel differential pair 2.
Display Port primary channel differential pair 2.
LVDS
LVDS
LVDS
Connect to LVDS connector
Connect to LVDS connector
Connect to LVDS connector
LVDS
LVDS
LVDS
