Denon DCD-F109, Руководство по обслуживанию

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73
PCM1796DBR (IC602)
PCM1796DBR Block Diagram
SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006
www.ti.com
5
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at T
A
= 25 ° C, V
CC
1 = V
CC
2L = V
CC
2R = 5 V, V
DD
= 3.3 V, f
S
= 44.1 kHz, system clock = 256 f
S
, and 24-bit data unless
otherwise noted
PARAMETER TEST CONDITIONS
PCM1796DB
UNIT PARAMETER TEST CONDITIONS
MIN TYP MAX
UNIT
POWER SUPPLY REQUIREMENTS
VDD 3 3.3 3.6 VDC
VCC1
Voltage range
VCC2L
Voltage range
4.75 5 5.25 VDC
VCC2R
(1)
fS = 44.1 kHz 7 9
IDD
(1)
fS = 96 kHz 13
mA IDD
Supply current (1)
fS = 192 kHz 25
mA
Supply current (1)
fS = 44.1 kHz 18 23
ICC
fS = 96 kHz 19
mA ICC
fS = 192 kHz 20
mA
(1)
fS = 44.1 kHz 115 150
Power dissipation (1)
fS = 96 kHz 140
mW Power dissipation (1)
fS = 192 kHz 180
mW
TEMPERATURE RANGE
Operation temperature –25 85 ° C
θ
JA
Thermal resistance 28-pin SSOP 100 ° C/W
(1)
Input is BPZ data.
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14 28
27
26
25
24
23
22
21
20
19
18
17
16
15
ZEROL
ZEROR
MSEL
LRCK
DATA
BCK
SCK
DGND
V
DD
MS
MDI
MC
MDO
RST
V
CC
2L
AGND3L
I
OUT
L–
I
OUT
L+
AGND2
V
CC
1
V
COM
L
V
COM
R
I
REF
AGND1
I
OUT
R–
I
OUT
R+
AGND3R
V
CC
2R
PCM1796
(TOP VIEW)
SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006
www.ti.com
7
FUNCTIONAL BLOCK DIAGRAM
Power Supply
RST
SCK
Advanced
Segment
DAC
Modulator
IOUTL+
IOUTL–
IOUTR–
Current
Segment
DAC
IOUTR+
Bias
and
Vref
VCOML
VCOMR
AGND2
V DD
V CC
1
V CC
2L
V CC
2R
AGND1
I/V and Filter
8
Oversampling
Digital
Filter
and
Function
Control
Audio
Data Input
I/F
LRCK
BCK
DATA
MDO
MDI
MC
MS
AGND3L
AGND3R
DGND
Current
Segment
DAC
IREF
VOUTL
I/V and Filter
VOUTR
Function
Control
I/F
MSEL
Zero
Detect
ZEROL
ZEROR
System
Clock
Manager