Denon AVR-S910W, Руководство по обслуживанию

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AD8195ACPZ (HDMI : U1022)
AD8195ACPZ Terminl Function
AD8195ACPZ Block diagram
NOTES
1. THE AD8195 LFCSP HAS AN EXPOSED PAD ON THE UNDERSIDE OF
THE PACKAGE THAT AIDS IN HEAT DISSIPATION. THE PAD MUST BE
ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER
TO MEET THERMAL SPECIFICATIONS.
AD8195
TOP VIEW
(Not to Scale)
1 IN0
2 IP0
3 IN1
4 IP1
5 VTTI
6 IN2
7 IP2
10 AVCC
30 AVCC
29 PE_EN
28 TX_EN
27 AVEE
26 AVCC
25 AVCC
24 AVEE
21 COMP
4
0
S
C
L
_
IN
3
9
S
DA_
IN
3
8
C
E
C_
IN
3
7
A
VE
E
3
6
V
R
E
F
_
IN
3
5
S
C
L
_
O
U
T
3
4
S
DA_
O
U
T
3
1
C
E
C_
O
U
T
1
1
O
N
0
1
2
O
P
0
1
3
V
T
T
O
1
4
O
N
1
1
5
O
P
1
1
6
A
V
C
C
1
7
O
N
2
2
0
O
P
3
9 IP3
8 IN3
22 AVCC
23 AVCC
1
9
O
N
3
1
8
O
P
2
3
2
A
M
U
XV
C
C
3
3
V
R
E
F
_
O
U
T
PIN 1
INDICATOR
0
7
0
4
9
-0
0
3
AD8195
Rev. 0 | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. THE AD8195 LFCSP HAS AN EXPOSED PAD ON THE UNDERSIDE OF
THE PACKAGE THAT AIDS IN HEAT DISSIPATION. THE PAD MUST BE
ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER
TO MEET THERMAL SPECIFICATIONS.
AD8195
TOP VIEW
(Not to Scale)
1 IN0
2 IP0
3 IN1
4 IP1
5 VTTI
6 IN2
7 IP2
10 AVCC
30 AVCC
29 PE_EN
28 TX_EN
27 AVEE
26 AVCC
25 AVCC
24 AVEE
21 COMP
40
S
C
L
_
IN
39
S
DA_I
N
38
CE
C_I
N
3
7
A
VEE
36
V
R
E
F
_I
N
3
5
S
CL
_
O
UT
34
S
DA_O
U
T
31
CE
C_O
U
T
11
O
N0
12
O
P0
13
VT
T
O
14
O
N1
15
O
P1
16
AV
CC
17
O
N2
20
O
P3
9 IP3
8 IN3
22 AVCC
23 AVCC
19
O
N3
18
O
P2
3
2
AM
U
X
V
CC
33
V
R
E
F
_O
U
T
PIN 1
INDICATOR
07
04
9-
00
3
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type 1 Description
1 IN0 HS I High Speed Input Complement.
2 IP0 HS I High Speed Input.
3 IN1 HS I High Speed Input Complement.
4 IP1 HS I High Speed Input.
5 VTTI Power Input Termination Supply. Nominally connected to AVCC.
6 IN2 HS I High Speed Input Complement.
7 IP2 HS I High Speed Input.
8 IN3 HS I High Speed Input Complement.
9 IP3 HS I High Speed Input.
10, 16, 22, 23, 25, 26, 30 AVCC Power Positive Analog Supply. 3.3 V nominal.
11 ON0 HS O High Speed Output Complement.
12 OP0 HS O High Speed Output.
13 VTTO Power Output Termination Supply. Nominally connected to AVCC.
14 ON1 HS O High Speed Output Complement.
15 OP1 HS O High Speed Output.
17 ON2 HS O High Speed Output Complement.
18 OP2 HS O High Speed Output.
19 ON3 HS O High Speed Output Complement.
20 OP3 HS O High Speed Output.
21 COMP Control Power-On Compensation Pin. Bypass to ground through a 10 μF capacitor.
24, 27, 37, Exposed Pad AVEE Power Negative Analog Supply. 0 V nominal.
28 TX_EN Control High Speed Output Enable Parallel Interface.
29 PE_EN Control High Speed Preemphasis Enable Parallel Interface.
31 CEC_OUT LS I/O CEC Output Side.
32 AMUXVCC Power Positive Auxiliary Buffer Supply. 5 V nominal.
IP[3:0]
IN[3:0]
VTTI
OP[3:0]
AMUXVCC
AVEE
VTTO
AVCC
ON[3:0]
VREF_IN VREF_OUT
+
–
+
–
EQ
BUFFER
PE
CONTROL
LOGIC
4
4
4
2 2
4
HIGH SPEED BUFFERED
LOW SPEED BUFFERED
P
E
_
E
N
T
X
_
E
N
C
O
M
P
PARALLEL
BIDIRECTIONAL
AD8195
SCL_IN
SDA_IN
SCL_OUT
SDA_OUT
CEC_IN CEC_OUT
148