DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 88 of 242
Field
Description of fields within Register file: 0x0F – System Event Status Register
RXPHE
reg:0F:00
bit:12
Receiver PHY Header Error. This event status bit is set to indicate that the receiver has found a
non-correctable error in the PHR. The PHR includes a SECDED error check sequence (see
section 10.4) that can correct a single bit error and detect a double bit error. The double error
is not correctable and its detection is the event that the RXPHE event status flag is notifying.
Generally this error means that correct frame reception is not possible, and so typically this
event will abort frame reception (depending on the DIS_PHE configuration in
) after which the receiver may return to preamble search (depending on
the RXAUTR configuration also in
Register file: 0x04 – System Configuration
gives details of the frame reception process. The RXPHE bit can be cleared
explicitly by writing a 1 to it. It is also automatically cleared by the next receiver enable,
including those caused by the RXAUTR auto-re-enable. PHY Header Error events are counted
in
Sub-Register 0x2F:04 – PHR Error Counter
, as long as counting is enabled by the EVC_EN bit
Sub-Register 0x2F:00 – Event Counter Control
RXDFR
reg:0F:00
bit:13
Receiver Data Frame Ready. This event status bit is set to indicate that the completion of the
frame reception process. Section 4
gives details of the frame reception
process. It is expected that this will be used as the main “Receive” (interrupt) event signalling
the completion of a frame reception, and, that the receive event processing routine will
examine the RXFCG and RXFCE to determine whether the frame has been received without
error (or not), and also to check the LDEDONE event status flag to validate the receive
timestamp information.
In order to ensure that the receive timestamp information is valid before any receive interrupt
processing takes place, the setting of RXDFR is delayed until the LDE adjustments of the
timestamp have completed, at which time the LDEDONE event status bit will be set (or possibly
LDEERR). The RXDFR event status flag bit is included in the RX double-buffered swinging-set. It
is automatically cleared by the RX enable. It can also be cleared explicitly by writing a 1 to it.
NOTE:
If the RXDFR is set, but neither RXFCG nor RXFCE events have been flagged and also
neither LDEDONE nor LDEERR have been flagged then the LDE code has not been loaded
correctly and is not running correctly. Please review 2.5.5.10.
RXFCG
reg:0F:00
bit:14
Receiver FCS Good. This event status bit reflects the result of the frame CRC checking. It is set
(or not) at the end of frame reception coincidentally with the setting of the RXDFR event status
flag.
When RXFCG is set to 1 it indicates that the CRC check result generated on the received data
matches with the 2-octet FCS sequence at the end of the frame. RXDFR with RXFCG then
indicates the correct reception a valid frame. The RXFCG bit is in the RX double-buffered
swinging-set. It is automatically cleared by RX enable. It can also be cleared explicitly by
writing a 1 to it.
RXFCE
reg:0F:00
bit:15
Receiver FCS Error. This event status bit also reflects the result of the frame CRC checking. It is
valid at the end of frame reception coincidentally with the setting of the RXDFR event status
flag.
When RXFCE is set to 1 it indicates that the CRC check result generated on the received data
FAILED to match with the 2-octet FCS sequence at the end of the frame. The RXFCE bit is
included in the RX double-buffered swinging-set. It is automatically cleared by RX enable. It
can also be cleared explicitly by writing a 1 to it. RXFCE events are also counted in
, as long as counting is enabled by the EVC_EN bit in
