DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 89 of 242
Field
Description of fields within Register file: 0x0F – System Event Status Register
RXRFSL
reg:0F:00
bit:16
Receiver Reed Solomon Frame Sync Loss. The RXRFSL event status bit is set to indicate that the
receiver has found a non-correctable error during the Reed Solomon decoding of the data
portion of the frame. Generally this means that correct frame reception is not possible, and so
typically this event will abort frame reception (depending on the DIS_RSDE configuration in
Register file: 0x04 – System Configuration
) after which the receiver may return to preamble
search (depending on the RXAUTR configuration also in
gives details of the frame reception process.
The RXRFSL bit can be cleared explicitly by writing a 1 to it. It is also automatically cleared by
the next receiver enable, including those caused by the RXAUTR auto-re-enable. Reed
Solomon Frame Sync Loss Error events are also counted in
Sub-Register 0x2F:06 – RSD Error
, as long as counting is enabled by the EVC_EN bit in
RXRFTO
reg:0F:00
bit:17
Receive Frame Wait Timeout. This event status bit is set to indicate that a receive frame wait
timeout has occurred. The receive frame wait timeout is enabled by the RXWTOE bit in
Register file: 0x04 – System Configuration
, with the timeout being set by
Receive Frame Wait Timeout Period
. The receive frame wait timeout starts running when the
receiver is enabled and stops running either when a valid frame is received or when the
timeout occurs and is signalled by this RXRFTO event status flag bit. The RXRFTO bit is
automatically cleared at the next receiver enable. It can also be cleared explicitly by writing a 1
to it. Receive frame wait timeout events are also counted in
Sub-Register 0x2F:14 – RX Frame
, as long as counting is enabled by the EVC_EN bit in
0x2F:00 – Event Counter Control
LDEERR
reg:0F:00
bit:18
Leading edge detection processing error. A large part of the leading edge detection algorithm
is a search in the channel impulse response to find the first arriving ray of the RMARKER. This
should be bounded and finish in a reasonably short time, but in case not, the LDE includes a
failsafe mechanism of a watchdog timer (60 µs) that is initialized at the start of each LDE
search (when a good PHR has been detected). We do not expect DW1000 users to ever see
this event, however if the watchdog timer expires before the LDE has completed its RX
timestamp adjustments then the LDE search will be aborted and the error will be reported by
the LDEERR event status flag. The LDEERR bit is automatically cleared at the next receiver
enable. It can also be cleared explicitly by writing a 1 to it.
–
reg:0F:00
bit:19
This bit is reserved.
RXOVRR
reg:0F:00
bit:20
Receiver Overrun. This event status bit only applies when double RX buffering is enabled (by
clearing the DIS_DRXB bit in
Register file: 0x04 – System Configuration
). The RXOVRR event flag
is set to indicate that an overrun error has occurred in the receiver. See section
4.3.5 –
for more details of double buffering and the use of this RXOVRR error flag. The
RXOVRR event status bit is a READ ONLY bit. It will clear when HRBPT is used to signal the
completion of processing for a receiver buffer, freeing that buffer for data reception. Receiver
Overrun events are also counted in
Sub-Register 0x2F:0E – RX Overrun Error Counter
, assuming
that counting is enabled by the EVC_EN bit in
